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// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
* Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/gpio/meson-a1-gpio.h>
/ {
compatible = "amlogic,a1";
interrupt-parent = <&gic>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <2>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
};
l2: l2-cache0 {
compatible = "cache";
cache-level = <2>;
cache-unified;
};
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
reserved-memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
linux,cma {
compatible = "shared-dma-pool";
reusable;
size = <0x0 0x800000>;
alignment = <0x0 0x400000>;
linux,cma-default;
};
};
sm: secure-monitor {
compatible = "amlogic,meson-gxbb-sm";
pwrc: power-controller {
compatible = "amlogic,meson-a1-pwrc";
#power-domain-cells = <1>;
status = "okay";
};
};
soc {
compatible = "simple-bus";
#address-cells = <2>;
#size-cells = <2>;
ranges;
apb: bus@fe000000 {
compatible = "simple-bus";
reg = <0x0 0xfe000000 0x0 0x1000000>;
#address-cells = <2>;
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
reset: reset-controller@0 {
compatible = "amlogic,meson-a1-reset";
reg = <0x0 0x0 0x0 0x8c>;
#reset-cells = <1>;
};
periphs_pinctrl: pinctrl@400 {
compatible = "amlogic,meson-a1-periphs-pinctrl";
#address-cells = <2>;
#size-cells = <2>;
ranges;
gpio: bank@400 {
reg = <0x0 0x0400 0x0 0x003c>,
<0x0 0x0480 0x0 0x0118>;
reg-names = "mux", "gpio";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&periphs_pinctrl 0 0 62>;
};
};
uart_AO: serial@1c00 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x1c00 0x0 0x18>;
interrupts = <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
uart_AO_B: serial@2000 {
compatible = "amlogic,meson-gx-uart",
"amlogic,meson-ao-uart";
reg = <0x0 0x2000 0x0 0x18>;
interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>, <&xtal>, <&xtal>;
clock-names = "xtal", "pclk", "baud";
status = "disabled";
};
gpio_intc: interrupt-controller@0440 {
compatible = "amlogic,meson-a1-gpio-intc",
"amlogic,meson-gpio-intc";
reg = <0x0 0x0440 0x0 0x14>;
interrupt-controller;
#interrupt-cells = <2>;
amlogic,channel-interrupts =
<49 50 51 52 53 54 55 56>;
};
};
gic: interrupt-controller@ff901000 {
compatible = "arm,gic-400";
reg = <0x0 0xff901000 0x0 0x1000>,
<0x0 0xff902000 0x0 0x2000>,
<0x0 0xff904000 0x0 0x2000>,
<0x0 0xff906000 0x0 0x2000>;
interrupt-controller;
interrupts = <GIC_PPI 9
(GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
#interrupt-cells = <3>;
#address-cells = <0>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 10
(GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
};
xtal: xtal-clk {
compatible = "fixed-clock";
clock-frequency = <24000000>;
clock-output-names = "xtal";
#clock-cells = <0>;
};
};
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