1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
|
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
/*
* (C) 2018 MediaTek Inc.
* Copyright (C) 2022 BayLibre SAS
* Fabien Parent <fparent@baylibre.com>
* Bernhard Rosenkränzer <bero@baylibre.com>
*/
#include <dt-bindings/clock/mediatek,mt8365-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/power/mediatek,mt8365-power.h>
/ {
compatible = "mediatek,mt8365";
interrupt-parent = <&sysirq>;
#address-cells = <2>;
#size-cells = <2>;
cpus {
#address-cells = <1>;
#size-cells = <0>;
cluster0_opp: opp-table-0 {
compatible = "operating-points-v2";
opp-shared;
opp-850000000 {
opp-hz = /bits/ 64 <850000000>;
opp-microvolt = <650000>;
};
opp-918000000 {
opp-hz = /bits/ 64 <918000000>;
opp-microvolt = <668750>;
};
opp-987000000 {
opp-hz = /bits/ 64 <987000000>;
opp-microvolt = <687500>;
};
opp-1056000000 {
opp-hz = /bits/ 64 <1056000000>;
opp-microvolt = <706250>;
};
opp-1125000000 {
opp-hz = /bits/ 64 <1125000000>;
opp-microvolt = <725000>;
};
opp-1216000000 {
opp-hz = /bits/ 64 <1216000000>;
opp-microvolt = <750000>;
};
opp-1308000000 {
opp-hz = /bits/ 64 <1308000000>;
opp-microvolt = <775000>;
};
opp-1400000000 {
opp-hz = /bits/ 64 <1400000000>;
opp-microvolt = <800000>;
};
opp-1466000000 {
opp-hz = /bits/ 64 <1466000000>;
opp-microvolt = <825000>;
};
opp-1533000000 {
opp-hz = /bits/ 64 <1533000000>;
opp-microvolt = <850000>;
};
opp-1633000000 {
opp-hz = /bits/ 64 <1633000000>;
opp-microvolt = <887500>;
};
opp-1700000000 {
opp-hz = /bits/ 64 <1700000000>;
opp-microvolt = <912500>;
};
opp-1767000000 {
opp-hz = /bits/ 64 <1767000000>;
opp-microvolt = <937500>;
};
opp-1834000000 {
opp-hz = /bits/ 64 <1834000000>;
opp-microvolt = <962500>;
};
opp-1917000000 {
opp-hz = /bits/ 64 <1917000000>;
opp-microvolt = <993750>;
};
opp-2001000000 {
opp-hz = /bits/ 64 <2001000000>;
opp-microvolt = <1025000>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&cpu0>;
};
core1 {
cpu = <&cpu1>;
};
core2 {
cpu = <&cpu2>;
};
core3 {
cpu = <&cpu3>;
};
};
};
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x0>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate";
operating-points-v2 = <&cluster0_opp>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x1>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x2>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
reg = <0x3>;
#cooling-cells = <2>;
enable-method = "psci";
cpu-idle-states = <&CPU_MCDI &CLUSTER_MCDI &CLUSTER_DPIDLE>;
i-cache-size = <0x8000>;
i-cache-line-size = <64>;
i-cache-sets = <256>;
d-cache-size = <0x8000>;
d-cache-line-size = <64>;
d-cache-sets = <256>;
next-level-cache = <&l2>;
clocks = <&mcucfg CLK_MCU_BUS_SEL>,
<&apmixedsys CLK_APMIXED_MAINPLL>;
clock-names = "cpu", "intermediate", "armpll";
operating-points-v2 = <&cluster0_opp>;
};
idle-states {
entry-method = "psci";
CPU_MCDI: cpu-mcdi {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x00010001>;
entry-latency-us = <300>;
exit-latency-us = <200>;
min-residency-us = <1000>;
};
CLUSTER_MCDI: cluster-mcdi {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x01010001>;
entry-latency-us = <350>;
exit-latency-us = <250>;
min-residency-us = <1200>;
};
CLUSTER_DPIDLE: cluster-dpidle {
compatible = "arm,idle-state";
local-timer-stop;
arm,psci-suspend-param = <0x01010004>;
entry-latency-us = <300>;
exit-latency-us = <800>;
min-residency-us = <3300>;
};
};
l2: l2-cache {
compatible = "cache";
cache-level = <2>;
cache-size = <0x80000>;
cache-line-size = <64>;
cache-sets = <512>;
cache-unified;
};
};
clk26m: oscillator {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <26000000>;
clock-output-names = "clk26m";
};
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
soc {
#address-cells = <2>;
#size-cells = <2>;
compatible = "simple-bus";
ranges;
gic: interrupt-controller@c000000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
interrupt-controller;
reg = <0 0x0c000000 0 0x10000>, /* GICD */
<0 0x0c080000 0 0x80000>, /* GICR */
<0 0x0c400000 0 0x2000>, /* GICC */
<0 0x0c410000 0 0x1000>, /* GICH */
<0 0x0c420000 0 0x2000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
};
topckgen: syscon@10000000 {
compatible = "mediatek,mt8365-topckgen", "syscon";
reg = <0 0x10000000 0 0x1000>;
#clock-cells = <1>;
};
infracfg: syscon@10001000 {
compatible = "mediatek,mt8365-infracfg", "syscon";
reg = <0 0x10001000 0 0x1000>;
#clock-cells = <1>;
};
pericfg: syscon@10003000 {
compatible = "mediatek,mt8365-pericfg", "syscon";
reg = <0 0x10003000 0 0x1000>;
#clock-cells = <1>;
};
syscfg_pctl: syscfg-pctl@10005000 {
compatible = "mediatek,mt8365-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
scpsys: syscon@10006000 {
compatible = "mediatek,mt8365-syscfg", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
#power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
compatible = "mediatek,mt8365-power-controller";
#address-cells = <1>;
#size-cells = <0>;
#power-domain-cells = <1>;
/* power domains of the SoC */
power-domain@MT8365_POWER_DOMAIN_MM {
reg = <MT8365_POWER_DOMAIN_MM>;
clocks = <&topckgen CLK_TOP_MM_SEL>,
<&mmsys CLK_MM_MM_SMI_COMMON>,
<&mmsys CLK_MM_MM_SMI_COMM0>,
<&mmsys CLK_MM_MM_SMI_COMM1>,
<&mmsys CLK_MM_MM_SMI_LARB0>;
clock-names = "mm", "mm-0", "mm-1",
"mm-2", "mm-3";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
mediatek,infracfg-nao = <&infracfg_nao>;
#address-cells = <1>;
#size-cells = <0>;
power-domain@MT8365_POWER_DOMAIN_CAM {
reg = <MT8365_POWER_DOMAIN_CAM>;
clocks = <&camsys CLK_CAM_LARB2>,
<&camsys CLK_CAM_SENIF>,
<&camsys CLK_CAMSV0>,
<&camsys CLK_CAMSV1>,
<&camsys CLK_CAM_FDVT>,
<&camsys CLK_CAM_WPE>;
clock-names = "cam-0", "cam-1",
"cam-2", "cam-3",
"cam-4", "cam-5";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_VDEC {
reg = <MT8365_POWER_DOMAIN_VDEC>;
#power-domain-cells = <0>;
};
power-domain@MT8365_POWER_DOMAIN_VENC {
reg = <MT8365_POWER_DOMAIN_VENC>;
#power-domain-cells = <0>;
};
power-domain@MT8365_POWER_DOMAIN_APU {
reg = <MT8365_POWER_DOMAIN_APU>;
clocks = <&infracfg CLK_IFR_APU_AXI>,
<&apu CLK_APU_IPU_CK>,
<&apu CLK_APU_AXI>,
<&apu CLK_APU_JTAG>,
<&apu CLK_APU_IF_CK>,
<&apu CLK_APU_EDMA>,
<&apu CLK_APU_AHB>;
clock-names = "apu", "apu-0",
"apu-1", "apu-2",
"apu-3", "apu-4",
"apu-5";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
power-domain@MT8365_POWER_DOMAIN_CONN {
reg = <MT8365_POWER_DOMAIN_CONN>;
clocks = <&topckgen CLK_TOP_CONN_32K>,
<&topckgen CLK_TOP_CONN_26M>;
clock-names = "conn", "conn1";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_MFG {
reg = <MT8365_POWER_DOMAIN_MFG>;
clocks = <&topckgen CLK_TOP_MFG_SEL>;
clock-names = "mfg";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_AUDIO {
reg = <MT8365_POWER_DOMAIN_AUDIO>;
clocks = <&topckgen CLK_TOP_AUD_INTBUS_SEL>,
<&infracfg CLK_IFR_AUDIO>,
<&infracfg CLK_IFR_AUD_26M_BK>;
clock-names = "audio", "audio1", "audio2";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
power-domain@MT8365_POWER_DOMAIN_DSP {
reg = <MT8365_POWER_DOMAIN_DSP>;
clocks = <&topckgen CLK_TOP_DSP_SEL>,
<&topckgen CLK_TOP_DSP_26M>;
clock-names = "dsp", "dsp1";
#power-domain-cells = <0>;
mediatek,infracfg = <&infracfg>;
};
};
};
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8365-wdt", "mediatek,mt6589-wdt";
reg = <0 0x10007000 0 0x100>;
#reset-cells = <1>;
};
pio: pinctrl@1000b000 {
compatible = "mediatek,mt8365-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
};
apmixedsys: syscon@1000c000 {
compatible = "mediatek,mt8365-apmixedsys", "syscon";
reg = <0 0x1000c000 0 0x1000>;
#clock-cells = <1>;
};
pwrap: pwrap@1000d000 {
compatible = "mediatek,mt8365-pwrap";
reg = <0 0x1000d000 0 0x1000>;
reg-names = "pwrap";
interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&infracfg CLK_IFR_PWRAP_SPI>,
<&infracfg CLK_IFR_PMIC_AP>,
<&infracfg CLK_IFR_PWRAP_SYS>,
<&infracfg CLK_IFR_PWRAP_TMR>;
clock-names = "spi", "wrap", "sys", "tmr";
};
keypad: keypad@10010000 {
compatible = "mediatek,mt6779-keypad";
reg = <0 0x10010000 0 0x1000>;
wakeup-source;
interrupts = <GIC_SPI 124 IRQ_TYPE_EDGE_FALLING>;
clocks = <&clk26m>;
clock-names = "kpd";
status = "disabled";
};
mcucfg: syscon@10200000 {
compatible = "mediatek,mt8365-mcucfg", "syscon";
reg = <0 0x10200000 0 0x2000>;
#clock-cells = <1>;
};
sysirq: interrupt-controller@10200a80 {
compatible = "mediatek,mt8365-sysirq", "mediatek,mt6577-sysirq";
interrupt-controller;
#interrupt-cells = <3>;
interrupt-parent = <&gic>;
reg = <0 0x10200a80 0 0x20>;
};
infracfg_nao: infracfg@1020e000 {
compatible = "mediatek,mt8365-infracfg", "syscon";
reg = <0 0x1020e000 0 0x1000>;
#clock-cells = <1>;
};
rng: rng@1020f000 {
compatible = "mediatek,mt8365-rng", "mediatek,mt7623-rng";
reg = <0 0x1020f000 0 0x100>;
clocks = <&infracfg CLK_IFR_TRNG>;
clock-names = "rng";
};
apdma: dma-controller@11000280 {
compatible = "mediatek,mt8365-uart-dma", "mediatek,mt6577-uart-dma";
reg = <0 0x11000280 0 0x80>,
<0 0x11000300 0 0x80>,
<0 0x11000380 0 0x80>,
<0 0x11000400 0 0x80>,
<0 0x11000580 0 0x80>,
<0 0x11000600 0 0x80>;
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 46 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 47 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 48 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 51 IRQ_TYPE_LEVEL_LOW>,
<GIC_SPI 52 IRQ_TYPE_LEVEL_LOW>;
dma-requests = <6>;
clocks = <&infracfg CLK_IFR_AP_DMA>;
clock-names = "apdma";
#dma-cells = <1>;
};
uart0: serial@11002000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11002000 0 0x1000>;
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART0>;
clock-names = "baud", "bus";
dmas = <&apdma 0>, <&apdma 1>;
dma-names = "tx", "rx";
status = "disabled";
};
uart1: serial@11003000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11003000 0 0x1000>;
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART1>;
clock-names = "baud", "bus";
dmas = <&apdma 2>, <&apdma 3>;
dma-names = "tx", "rx";
status = "disabled";
};
uart2: serial@11004000 {
compatible = "mediatek,mt8365-uart", "mediatek,mt6577-uart";
reg = <0 0x11004000 0 0x1000>;
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_LOW>;
clocks = <&clk26m>, <&infracfg CLK_IFR_UART2>;
clock-names = "baud", "bus";
dmas = <&apdma 4>, <&apdma 5>;
dma-names = "tx", "rx";
status = "disabled";
};
pwm: pwm@11006000 {
compatible = "mediatek,mt8365-pwm";
reg = <0 0x11006000 0 0x1000>;
#pwm-cells = <2>;
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_LOW>;
clocks = <&infracfg CLK_IFR_PWM_HCLK>,
<&infracfg CLK_IFR_PWM>,
<&infracfg CLK_IFR_PWM1>,
<&infracfg CLK_IFR_PWM2>,
<&infracfg CLK_IFR_PWM3>;
clock-names = "top", "main", "pwm1", "pwm2", "pwm3";
};
i2c0: i2c@11007000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11007000 0 0xa0>, <0 0x11000080 0 0x80>;
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C0_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c1: i2c@11008000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11008000 0 0xa0>, <0 0x11000100 0 0x80>;
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C1_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c2: i2c@11009000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x11009000 0 0xa0>, <0 0x11000180 0 0x80>;
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C2_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
spi: spi@1100a000 {
compatible = "mediatek,mt8365-spi", "mediatek,mt7622-spi";
reg = <0 0x1100a000 0 0x100>;
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_UNIVPLL2_D4>,
<&topckgen CLK_TOP_SPI_SEL>,
<&infracfg CLK_IFR_SPI0>;
clock-names = "parent-clk", "sel-clk", "spi-clk";
status = "disabled";
};
i2c3: i2c@1100f000 {
compatible = "mediatek,mt8365-i2c", "mediatek,mt8168-i2c";
reg = <0 0x1100f000 0 0xa0>, <0 0x11000200 0 0x80>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_LOW>;
clock-div = <1>;
clocks = <&infracfg CLK_IFR_I2C3_AXI>, <&infracfg CLK_IFR_AP_DMA>;
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
ssusb: usb@11201000 {
compatible = "mediatek,mt8365-mtu3", "mediatek,mtu3";
reg = <0 0x11201000 0 0x2e00>, <0 0x11203e00 0 0x0100>;
reg-names = "mac", "ippc";
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_LOW>;
phys = <&u2port0 PHY_TYPE_USB2>,
<&u2port1 PHY_TYPE_USB2>;
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
<&infracfg CLK_IFR_SSUSB_REF>,
<&infracfg CLK_IFR_SSUSB_SYS>,
<&infracfg CLK_IFR_ICUSB>;
clock-names = "sys_ck", "ref_ck", "mcu_ck", "dma_ck";
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
usb_host: usb@11200000 {
compatible = "mediatek,mt8365-xhci", "mediatek,mtk-xhci";
reg = <0 0x11200000 0 0x1000>;
reg-names = "mac";
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_SSUSB_TOP_CK_EN>,
<&infracfg CLK_IFR_SSUSB_REF>,
<&infracfg CLK_IFR_SSUSB_SYS>,
<&infracfg CLK_IFR_ICUSB>,
<&infracfg CLK_IFR_SSUSB_XHCI>;
clock-names = "sys_ck", "ref_ck", "mcu_ck",
"dma_ck", "xhci_ck";
status = "disabled";
};
};
mmc0: mmc@11230000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11230000 0 0x1000>,
<0 0x11cd0000 0 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>,
<&infracfg CLK_IFR_MSDC0_HCLK>,
<&infracfg CLK_IFR_MSDC0_SRC>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc1: mmc@11240000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11240000 0 0x1000>,
<0 0x11c90000 0 0x1000>;
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC30_1_SEL>,
<&infracfg CLK_IFR_MSDC1_HCLK>,
<&infracfg CLK_IFR_MSDC1_SRC>;
clock-names = "source", "hclk", "source_cg";
status = "disabled";
};
mmc2: mmc@11250000 {
compatible = "mediatek,mt8365-mmc", "mediatek,mt8183-mmc";
reg = <0 0x11250000 0 0x1000>,
<0 0x11c60000 0 0x1000>;
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_MSDC50_2_SEL>,
<&infracfg CLK_IFR_MSDC2_HCLK>,
<&infracfg CLK_IFR_MSDC2_SRC>,
<&infracfg CLK_IFR_MSDC2_BK>,
<&infracfg CLK_IFR_AP_MSDC0>;
clock-names = "source", "hclk", "source_cg",
"bus_clk", "sys_cg";
status = "disabled";
};
ethernet: ethernet@112a0000 {
compatible = "mediatek,mt8365-eth";
reg = <0 0x112a0000 0 0x1000>;
mediatek,pericfg = <&infracfg>;
interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&topckgen CLK_TOP_ETH_SEL>,
<&infracfg CLK_IFR_NIC_AXI>,
<&infracfg CLK_IFR_NIC_SLV_AXI>;
clock-names = "core", "reg", "trans";
status = "disabled";
};
u3phy: t-phy@11cc0000 {
compatible = "mediatek,mt8365-tphy", "mediatek,generic-tphy-v2";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0x11cc0000 0x9000>;
u2port0: usb-phy@0 {
reg = <0x0 0x400>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
<&topckgen CLK_TOP_USB20_48M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
u2port1: usb-phy@1000 {
reg = <0x1000 0x400>;
clocks = <&topckgen CLK_TOP_SSUSB_PHY_CK_EN>,
<&topckgen CLK_TOP_USB20_48M_EN>;
clock-names = "ref", "da_ref";
#phy-cells = <1>;
};
};
mmsys: syscon@14000000 {
compatible = "mediatek,mt8365-mmsys", "syscon";
reg = <0 0x14000000 0 0x1000>;
#clock-cells = <1>;
};
camsys: syscon@15000000 {
compatible = "mediatek,mt8365-imgsys", "syscon";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
apu: syscon@19020000 {
compatible = "mediatek,mt8365-apu", "syscon";
reg = <0 0x19020000 0 0x1000>;
#clock-cells = <1>;
};
};
timer {
compatible = "arm,armv8-timer";
interrupt-parent = <&gic>;
interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
};
system_clk: dummy13m {
compatible = "fixed-clock";
clock-frequency = <13000000>;
#clock-cells = <0>;
};
systimer: timer@10017000 {
compatible = "mediatek,mt8365-systimer", "mediatek,mt6765-timer";
reg = <0 0x10017000 0 0x100>;
interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&system_clk>;
clock-names = "clk13m";
};
};
|