summaryrefslogtreecommitdiffstats
path: root/arch/arm64/boot/dts/ti/k3-am62a7.dtsi
blob: 58f1c43edcf8f8962b607fa3eab9631198397223 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
// SPDX-License-Identifier: GPL-2.0
/*
 * Device Tree Source for AM62A7 SoC family in Quad core configuration
 *
 * TRM: https://www.ti.com/lit/zip/spruj16
 *
 * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
 */

/dts-v1/;

#include "k3-am62a.dtsi"

/ {
	cpus {
		#address-cells = <1>;
		#size-cells = <0>;

		cpu-map {
			cluster0: cluster0 {
				core0 {
					cpu = <&cpu0>;
				};

				core1 {
					cpu = <&cpu1>;
				};

				core2 {
					cpu = <&cpu2>;
				};

				core3 {
					cpu = <&cpu3>;
				};
			};
		};

		cpu0: cpu@0 {
			compatible = "arm,cortex-a53";
			reg = <0x000>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
		};

		cpu1: cpu@1 {
			compatible = "arm,cortex-a53";
			reg = <0x001>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
		};

		cpu2: cpu@2 {
			compatible = "arm,cortex-a53";
			reg = <0x002>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
		};

		cpu3: cpu@3 {
			compatible = "arm,cortex-a53";
			reg = <0x003>;
			device_type = "cpu";
			enable-method = "psci";
			i-cache-size = <0x8000>;
			i-cache-line-size = <64>;
			i-cache-sets = <256>;
			d-cache-size = <0x8000>;
			d-cache-line-size = <64>;
			d-cache-sets = <128>;
			next-level-cache = <&L2_0>;
		};
	};

	L2_0: l2-cache0 {
		compatible = "cache";
		cache-unified;
		cache-level = <2>;
		cache-size = <0x80000>;
		cache-line-size = <64>;
		cache-sets = <512>;
	};
};