1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
|
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* UFS PHY driver for Samsung EXYNOS SoC
*
* Copyright (C) 2020 Samsung Electronics Co., Ltd.
* Author: Seungwon Jeon <essuuj@gmail.com>
* Author: Alim Akhtar <alim.akhtar@samsung.com>
*
*/
#ifndef _PHY_SAMSUNG_UFS_
#define _PHY_SAMSUNG_UFS_
#include <linux/phy/phy.h>
#include <linux/regmap.h>
#define PHY_COMN_BLK 1
#define PHY_TRSV_BLK 2
#define END_UFS_PHY_CFG { 0 }
#define PHY_TRSV_CH_OFFSET 0x30
#define PHY_APB_ADDR(off) ((off) << 2)
#define PHY_COMN_REG_CFG(o, v, d) { \
.off_0 = PHY_APB_ADDR((o)), \
.off_1 = 0, \
.val = (v), \
.desc = (d), \
.id = PHY_COMN_BLK, \
}
#define PHY_TRSV_REG_CFG_OFFSET(o, v, d, c) { \
.off_0 = PHY_APB_ADDR((o)), \
.off_1 = PHY_APB_ADDR((o) + (c)), \
.val = (v), \
.desc = (d), \
.id = PHY_TRSV_BLK, \
}
#define PHY_TRSV_REG_CFG(o, v, d) \
PHY_TRSV_REG_CFG_OFFSET(o, v, d, PHY_TRSV_CH_OFFSET)
/* UFS PHY registers */
#define PHY_PLL_LOCK_STATUS 0x1e
#define PHY_CDR_LOCK_STATUS 0x5e
#define PHY_PLL_LOCK_BIT BIT(5)
#define PHY_CDR_LOCK_BIT BIT(4)
/* description for PHY calibration */
enum {
/* applicable to any */
PWR_DESC_ANY = 0,
/* mode */
PWR_DESC_PWM = 1,
PWR_DESC_HS = 2,
/* series */
PWR_DESC_SER_A = 1,
PWR_DESC_SER_B = 2,
/* gear */
PWR_DESC_G1 = 1,
PWR_DESC_G2 = 2,
PWR_DESC_G3 = 3,
/* field mask */
MD_MASK = 0x3,
SR_MASK = 0x3,
GR_MASK = 0x7,
};
#define PWR_MODE_HS_G1_ANY PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_ANY)
#define PWR_MODE_HS_G1_SER_A PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_A)
#define PWR_MODE_HS_G1_SER_B PWR_MODE_HS(PWR_DESC_G1, PWR_DESC_SER_B)
#define PWR_MODE_HS_G2_ANY PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_ANY)
#define PWR_MODE_HS_G2_SER_A PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_A)
#define PWR_MODE_HS_G2_SER_B PWR_MODE_HS(PWR_DESC_G2, PWR_DESC_SER_B)
#define PWR_MODE_HS_G3_ANY PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_ANY)
#define PWR_MODE_HS_G3_SER_A PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_A)
#define PWR_MODE_HS_G3_SER_B PWR_MODE_HS(PWR_DESC_G3, PWR_DESC_SER_B)
#define PWR_MODE(g, s, m) ((((g) & GR_MASK) << 4) |\
(((s) & SR_MASK) << 2) | ((m) & MD_MASK))
#define PWR_MODE_PWM_ANY PWR_MODE(PWR_DESC_ANY,\
PWR_DESC_ANY, PWR_DESC_PWM)
#define PWR_MODE_HS(g, s) ((((g) & GR_MASK) << 4) |\
(((s) & SR_MASK) << 2) | PWR_DESC_HS)
#define PWR_MODE_HS_ANY PWR_MODE(PWR_DESC_ANY,\
PWR_DESC_ANY, PWR_DESC_HS)
#define PWR_MODE_ANY PWR_MODE(PWR_DESC_ANY,\
PWR_DESC_ANY, PWR_DESC_ANY)
/* PHY calibration point/state */
enum {
CFG_PRE_INIT,
CFG_POST_INIT,
CFG_PRE_PWR_HS,
CFG_POST_PWR_HS,
CFG_TAG_MAX,
};
struct samsung_ufs_phy_cfg {
u32 off_0;
u32 off_1;
u32 val;
u8 desc;
u8 id;
};
struct samsung_ufs_phy_drvdata {
const struct samsung_ufs_phy_cfg **cfg;
struct pmu_isol {
u32 offset;
u32 mask;
u32 en;
} isol;
bool has_symbol_clk;
};
struct samsung_ufs_phy {
struct device *dev;
void __iomem *reg_pma;
struct regmap *reg_pmu;
struct clk *ref_clk;
struct clk *ref_clk_parent;
struct clk *tx0_symbol_clk;
struct clk *rx0_symbol_clk;
struct clk *rx1_symbol_clk;
const struct samsung_ufs_phy_drvdata *drvdata;
struct samsung_ufs_phy_cfg **cfg;
const struct pmu_isol *isol;
u8 lane_cnt;
int ufs_phy_state;
enum phy_mode mode;
};
static inline struct samsung_ufs_phy *get_samsung_ufs_phy(struct phy *phy)
{
return (struct samsung_ufs_phy *)phy_get_drvdata(phy);
}
static inline void samsung_ufs_phy_ctrl_isol(
struct samsung_ufs_phy *phy, u32 isol)
{
regmap_update_bits(phy->reg_pmu, phy->isol->offset,
phy->isol->mask, isol ? 0 : phy->isol->en);
}
extern const struct samsung_ufs_phy_drvdata exynos7_ufs_phy;
extern const struct samsung_ufs_phy_drvdata exynosautov9_ufs_phy;
#endif /* _PHY_SAMSUNG_UFS_ */
|
