blob: e0d096607fefbaf4f9ee93921046ec675a9af05f (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
|
# SPDX-License-Identifier: GPL-2.0-only
#
# QE Communication options
#
config QUICC_ENGINE
bool "QUICC Engine (QE) framework support"
depends on OF && HAS_IOMEM
depends on PPC || ARM || ARM64 || COMPILE_TEST
select GENERIC_ALLOCATOR
select CRC32
help
The QUICC Engine (QE) is a new generation of communications
coprocessors on Freescale embedded CPUs (akin to CPM in older chips).
Selecting this option means that you wish to build a kernel
for a machine with a QE coprocessor.
config UCC_SLOW
bool
default y if SERIAL_QE
help
This option provides qe_lib support to UCC slow
protocols: UART, BISYNC, QMC
config UCC_FAST
bool
default y if UCC_GETH || QE_TDM
help
This option provides qe_lib support to UCC fast
protocols: HDLC, Ethernet, ATM, transparent
config UCC
bool
default y if UCC_FAST || UCC_SLOW
config CPM_TSA
tristate "CPM TSA support"
depends on OF && HAS_IOMEM
depends on CPM1 || (CPM && COMPILE_TEST)
help
Freescale CPM Time Slot Assigner (TSA)
controller.
This option enables support for this
controller
config CPM_QMC
tristate "CPM QMC support"
depends on OF && HAS_IOMEM
depends on CPM1 || (FSL_SOC && CPM && COMPILE_TEST)
depends on CPM_TSA
help
Freescale CPM QUICC Multichannel Controller
(QMC)
This option enables support for this
controller
config QE_TDM
bool
default y if FSL_UCC_HDLC
config QE_USB
bool
default y if USB_FSL_QE
help
QE USB Controller support
|