1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
|
[
{
"EventName": "ls_bad_status2.stli_other",
"EventCode": "0x24",
"BriefDescription": "Store-to-load conflicts (load unable to complete due to a non-forwardable conflict with an older store).",
"UMask": "0x02"
},
{
"EventName": "ls_locks.bus_lock",
"EventCode": "0x25",
"BriefDescription": "Retired Lock instructions which caused a bus lock.",
"UMask": "0x01"
},
{
"EventName": "ls_ret_cl_flush",
"EventCode": "0x26",
"BriefDescription": "Retired CLFLUSH instructions."
},
{
"EventName": "ls_ret_cpuid",
"EventCode": "0x27",
"BriefDescription": "Retired CPUID instructions."
},
{
"EventName": "ls_dispatch.ld_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory load operations dispatched to the load-store unit.",
"UMask": "0x01"
},
{
"EventName": "ls_dispatch.store_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory store operations dispatched to the load-store unit.",
"UMask": "0x02"
},
{
"EventName": "ls_dispatch.ld_st_dispatch",
"EventCode": "0x29",
"BriefDescription": "Number of memory load-store operations dispatched to the load-store unit.",
"UMask": "0x04"
},
{
"EventName": "ls_dispatch.all",
"EventCode": "0x29",
"BriefDescription": "Number of memory operations dispatched to the load-store unit.",
"UMask": "0x07"
},
{
"EventName": "ls_smi_rx",
"EventCode": "0x2b",
"BriefDescription": "SMIs received."
},
{
"EventName": "ls_int_taken",
"EventCode": "0x2c",
"BriefDescription": "Interrupts taken."
},
{
"EventName": "ls_stlf",
"EventCode": "0x35",
"BriefDescription": "Store-to-load-forward (STLF) hits."
},
{
"EventName": "ls_st_commit_cancel2.st_commit_cancel_wcb_full",
"EventCode": "0x37",
"BriefDescription": "Non-cacheable store commits cancelled due to the non-cacheable commit buffer being full.",
"UMask": "0x01"
},
{
"EventName": "ls_mab_alloc.load_store_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for load-store allocations.",
"UMask": "0x3f"
},
{
"EventName": "ls_mab_alloc.hardware_prefetcher_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for hardware prefetcher allocations.",
"UMask": "0x40"
},
{
"EventName": "ls_mab_alloc.all_allocations",
"EventCode": "0x41",
"BriefDescription": "Miss Address Buffer (MAB) entries allocated by a Load-Store (LS) pipe for all types of allocations.",
"UMask": "0x7f"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_l2",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_ccx",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_dmnd_fills_from_sys.local_all",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from local L2 cache, L3 cache or different L2 cache in the same CCX.",
"UMask": "0x03"
},
{
"EventName": "ls_dmnd_fills_from_sys.near_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_near",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_dmnd_fills_from_sys.far_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_dmnd_fills_from_sys.remote_cache",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from cache of another CCX when the address was in the same or a different NUMA node.",
"UMask": "0x14"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_far",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_dmnd_fills_from_sys.dram_io_all",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either DRAM or MMIO in the same or a different NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_dmnd_fills_from_sys.far_all",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket).",
"UMask": "0x50"
},
{
"EventName": "ls_dmnd_fills_from_sys.alternate_memories",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_dmnd_fills_from_sys.all",
"EventCode": "0x43",
"BriefDescription": "Demand data cache fills from all types of data sources.",
"UMask": "0xff"
},
{
"EventName": "ls_any_fills_from_sys.local_l2",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_any_fills_from_sys.local_ccx",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_any_fills_from_sys.local_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from local L2 cache or L3 cache or different L2 cache in the same CCX.",
"UMask": "0x03"
},
{
"EventName": "ls_any_fills_from_sys.near_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_near",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_any_fills_from_sys.far_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_any_fills_from_sys.remote_cache",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from cache of another CCX when the address was in the same or a different NUMA node.",
"UMask": "0x14"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_far",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_any_fills_from_sys.dram_io_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either DRAM or MMIO in any NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_any_fills_from_sys.far_all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket).",
"UMask": "0x50"
},
{
"EventName": "ls_any_fills_from_sys.alternate_memories",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_any_fills_from_sys.all",
"EventCode": "0x44",
"BriefDescription": "Any data cache fills from all types of data sources.",
"UMask": "0xff"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 4k pages.",
"UMask": "0x01"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x02"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 2M pages.",
"UMask": "0x04"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_hit",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB hits for 1G pages.",
"UMask": "0x08"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_4k_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 4k pages.",
"UMask": "0x10"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_coalesced_page_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for coalesced pages. A coalesced page is a 16k page created from four adjacent 4k pages.",
"UMask": "0x20"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_2m_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 2M pages.",
"UMask": "0x40"
},
{
"EventName": "ls_l1_d_tlb_miss.tlb_reload_1g_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for 1G pages.",
"UMask": "0x80"
},
{
"EventName": "ls_l1_d_tlb_miss.all_l2_miss",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses with L2 DTLB misses (page-table walks are requested) for all page sizes.",
"UMask": "0xf0"
},
{
"EventName": "ls_l1_d_tlb_miss.all",
"EventCode": "0x45",
"BriefDescription": "L1 DTLB misses for all page sizes.",
"UMask": "0xff"
},
{
"EventName": "ls_misal_loads.ma64",
"EventCode": "0x47",
"BriefDescription": "64B misaligned (cacheline crossing) loads.",
"UMask": "0x01"
},
{
"EventName": "ls_misal_loads.ma4k",
"EventCode": "0x47",
"BriefDescription": "4kB misaligned (page crossing) loads.",
"UMask": "0x02"
},
{
"EventName": "ls_pref_instr_disp.prefetch",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchT0 (move data to all cache levels), T1 (move data to all cache levels except L1) and T2 (move data to all cache levels except L1 and L2).",
"UMask": "0x01"
},
{
"EventName": "ls_pref_instr_disp.prefetch_w",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchW (move data to L1 cache and mark it modifiable).",
"UMask": "0x02"
},
{
"EventName": "ls_pref_instr_disp.prefetch_nta",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of type PrefetchNTA (move data with minimum cache pollution i.e. non-temporal access).",
"UMask": "0x04"
},
{
"EventName": "ls_pref_instr_disp.all",
"EventCode": "0x4b",
"BriefDescription": "Software prefetch instructions dispatched (speculative) of all types.",
"UMask": "0x07"
},
{
"EventName": "wcb_close.full_line_64b",
"EventCode": "0x50",
"BriefDescription": "Number of events that caused a Write Combining Buffer (WCB) entry to close because all 64 bytes of the entry have been written to.",
"UMask": "0x01"
},
{
"EventName": "ls_inef_sw_pref.data_pipe_sw_pf_dc_hit",
"EventCode": "0x52",
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a data cache hit.",
"UMask": "0x01"
},
{
"EventName": "ls_inef_sw_pref.mab_mch_cnt",
"EventCode": "0x52",
"BriefDescription": "Software prefetches that did not fetch data outside of the processor core as the PREFETCH instruction saw a match on an already allocated Miss Address Buffer (MAB).",
"UMask": "0x02"
},
{
"EventName": "ls_inef_sw_pref.all",
"EventCode": "0x52",
"BriefDescript6ion": "Software prefetches that did not fetch data outside of the processor core for any reason.",
"UMask": "0x03"
},
{
"EventName": "ls_sw_pf_dc_fills.local_l2",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_sw_pf_dc_fills.local_ccx",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_sw_pf_dc_fills.local_all",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from local L2 cache, L3 cache or different L2 cache in the same CCX.",
"UMask": "0x03"
},
{
"EventName": "ls_sw_pf_dc_fills.near_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_near",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_sw_pf_dc_fills.far_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_sw_pf_dc_fills.remote_cache",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from cache of another CCX when the address was in the same or a different NUMA node.",
"UMask": "0x14"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_far",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_sw_pf_dc_fills.dram_io_all",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either DRAM or MMIO in the same or a different NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_sw_pf_dc_fills.far_all",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket).",
"UMask": "0x50"
},
{
"EventName": "ls_sw_pf_dc_fills.alternate_memories",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_sw_pf_dc_fills.all",
"EventCode": "0x59",
"BriefDescription": "Software prefetch data cache fills from all types of data sources.",
"UMask": "0xdf"
},
{
"EventName": "ls_hw_pf_dc_fills.local_l2",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from local L2 cache.",
"UMask": "0x01"
},
{
"EventName": "ls_hw_pf_dc_fills.local_ccx",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from L3 cache or different L2 cache in the same CCX.",
"UMask": "0x02"
},
{
"EventName": "ls_hw_pf_dc_fills.local_all",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from local L2 cache, L3 cache or different L2 cache in the same CCX.",
"UMask": "0x03"
},
{
"EventName": "ls_hw_pf_dc_fills.near_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in the same NUMA node.",
"UMask": "0x04"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_near",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in the same NUMA node.",
"UMask": "0x08"
},
{
"EventName": "ls_hw_pf_dc_fills.far_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in a different NUMA node.",
"UMask": "0x10"
},
{
"EventName": "ls_hw_pf_dc_fills.remote_cache",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from cache of another CCX when the address was in the same or a different NUMA node.",
"UMask": "0x14"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_far",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in a different NUMA node (same or different socket).",
"UMask": "0x40"
},
{
"EventName": "ls_hw_pf_dc_fills.dram_io_all",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either DRAM or MMIO in the same or a different NUMA node (same or different socket).",
"UMask": "0x48"
},
{
"EventName": "ls_hw_pf_dc_fills.far_all",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from either cache of another CCX, DRAM or MMIO when the address was in a different NUMA node (same or different socket).",
"UMask": "0x50"
},
{
"EventName": "ls_hw_pf_dc_fills.alternate_memories",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from extension memory.",
"UMask": "0x80"
},
{
"EventName": "ls_hw_pf_dc_fills.all",
"EventCode": "0x5a",
"BriefDescription": "Hardware prefetch data cache fills from all types of data sources.",
"UMask": "0xdf"
},
{
"EventName": "ls_alloc_mab_count",
"EventCode": "0x5f",
"BriefDescription": "In-flight L1 data cache misses i.e. Miss Address Buffer (MAB) allocations each cycle."
},
{
"EventName": "ls_not_halted_cyc",
"EventCode": "0x76",
"BriefDescription": "Core cycles not in halt."
},
{
"EventName": "ls_tlb_flush.all",
"EventCode": "0x78",
"BriefDescription": "All TLB Flushes.",
"UMask": "0xff"
},
{
"EventName": "ls_not_halted_p0_cyc.p0_freq_cyc",
"EventCode": "0x120",
"BriefDescription": "Reference cycles (P0 frequency) not in halt .",
"UMask": "0x1"
}
]
|
