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| author | Gregory CLEMENT <gregory.clement@bootlin.com> | 2020-11-25 08:19:18 +0100 |
|---|---|---|
| committer | Sebastian Reichel <sebastian.reichel@collabora.com> | 2020-11-29 22:34:07 +0100 |
| commit | 01b8f5b53e4df5d22d0e273fea5124a972e8d5c4 (patch) | |
| tree | 56993a61bc450127beb940855deef60006a6d78f | |
| parent | Linux 5.10-rc1 (diff) | |
| download | linux-01b8f5b53e4df5d22d0e273fea5124a972e8d5c4.tar.xz linux-01b8f5b53e4df5d22d0e273fea5124a972e8d5c4.zip | |
dt-bindings: reset: ocelot: Add Luton and Jaguar2 support
This adds the support for 2 others MIPS based VCore III SoCs: Luton
and Jaguar2.
Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
| -rw-r--r-- | Documentation/devicetree/bindings/power/reset/ocelot-reset.txt | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt index 4d530d815484..c5de7b555feb 100644 --- a/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt +++ b/Documentation/devicetree/bindings/power/reset/ocelot-reset.txt @@ -7,7 +7,9 @@ The reset registers are both present in the MSCC vcoreiii MIPS and microchip Sparx5 armv8 SoC's. Required Properties: - - compatible: "mscc,ocelot-chip-reset" or "microchip,sparx5-chip-reset" + + - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset", + "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset" Example: reset@1070008 { |