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| author | Conor Dooley <conor.dooley@microchip.com> | 2023-12-08 17:06:51 +0100 |
|---|---|---|
| committer | Palmer Dabbelt <palmer@rivosinc.com> | 2024-01-11 16:36:29 +0100 |
| commit | 07df87c0f8815898cb994408c4b6dd542a1394b8 (patch) | |
| tree | ef5baf3fe879f9916e78673658daed490250de4f | |
| parent | dt-bindings: riscv: cpus: Clarify mmu-type interpretation (diff) | |
| download | linux-07df87c0f8815898cb994408c4b6dd542a1394b8.tar.xz linux-07df87c0f8815898cb994408c4b6dd542a1394b8.zip | |
dt-bindings: riscv: permit numbers in "riscv,isa"
There are some extensions that contain numbers, such as Zve32f, which
are enabled by the "max" cpu type in QEMU.
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231208-uncolored-oxidant-5ab37dd3ab84@spud
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
| -rw-r--r-- | Documentation/devicetree/bindings/riscv/extensions.yaml | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 27beedb98198..63d81dc895e5 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -48,7 +48,7 @@ properties: insensitive, letters in the riscv,isa string must be all lowercase. $ref: /schemas/types.yaml#/definitions/string - pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[a-z])+)?(?:_[hsxz](?:[a-z])+)*$ + pattern: ^rv(?:64|32)imaf?d?q?c?b?k?j?p?v?h?(?:[hsxz](?:[0-9a-z])+)?(?:_[hsxz](?:[0-9a-z])+)*$ deprecated: true riscv,isa-base: |