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| author | Dmitry Baryshkov <dmitry.baryshkov@linaro.org> | 2023-01-11 07:03:51 +0100 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-01-19 01:27:35 +0100 |
| commit | 0df0a8f2d2e2ebf107db88377493ff5f0da9d528 (patch) | |
| tree | ac2997312210cccd3fea2f4d57fb86282a0aacf2 | |
| parent | clk: qcom: ipq8074: populate fw_name for usb3phy-s (diff) | |
| download | linux-0df0a8f2d2e2ebf107db88377493ff5f0da9d528.tar.xz linux-0df0a8f2d2e2ebf107db88377493ff5f0da9d528.zip | |
dt-bindings: clock: qcom,gcc-apq8084: define clocks/clock-names
Define clock/clock-names properties of the GCC device node to be used
on APQ8084 platform.
Note: the driver uses a single pcie_pipe clock, however most probably
there are two pipe clocks, one from each of PCIe QMP PHYs.
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230111060402.1168726-2-dmitry.baryshkov@linaro.org
| -rw-r--r-- | Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml index 8ade176c24f4..d84608269080 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml @@ -25,6 +25,30 @@ properties: compatible: const: qcom,gcc-apq8084 + clocks: + items: + - description: XO source + - description: Sleep clock source + - description: UFS RX symbol 0 clock + - description: UFS RX symbol 1 clock + - description: UFS TX symbol 0 clock + - description: UFS TX symbol 1 clock + - description: SATA ASIC0 clock + - description: SATA RX clock + - description: PCIe PIPE clock + + clock-names: + items: + - const: xo + - const: sleep_clk + - const: ufs_rx_symbol_0_clk_src + - const: ufs_rx_symbol_1_clk_src + - const: ufs_tx_symbol_0_clk_src + - const: ufs_tx_symbol_1_clk_src + - const: sata_asic0_clk + - const: sata_rx_clk + - const: pcie_pipe + required: - compatible @@ -32,11 +56,31 @@ unevaluatedProperties: false examples: - | + /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */ clock-controller@fc400000 { compatible = "qcom,gcc-apq8084"; reg = <0xfc400000 0x4000>; #clock-cells = <1>; #reset-cells = <1>; #power-domain-cells = <1>; + + clocks = <&xo_board>, + <&sleep_clk>, + <&ufsphy 0>, + <&ufsphy 1>, + <&ufsphy 2>, + <&ufsphy 3>, + <&sata 0>, + <&sata 1>, + <&pcie_phy>; + clock-names = "xo", + "sleep_clk", + "ufs_rx_symbol_0_clk_src", + "ufs_rx_symbol_1_clk_src", + "ufs_tx_symbol_0_clk_src", + "ufs_tx_symbol_1_clk_src", + "sata_asic0_clk", + "sata_rx_clk", + "pcie_pipe"; }; ... |