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| author | Hans de Goede <hdegoede@redhat.com> | 2018-12-01 12:31:46 +0100 |
|---|---|---|
| committer | Hans de Goede <hdegoede@redhat.com> | 2019-01-21 10:45:25 +0100 |
| commit | 24bf86ccf9f5563f7d288f8b7672b0facdefbc95 (patch) | |
| tree | f8cd2da7d941a4b78ef9006898b6a3d300508bb3 | |
| parent | drm/i915/dsi: Fix pipe_bpp for handling for 6 bpc pixel-formats (diff) | |
| download | linux-24bf86ccf9f5563f7d288f8b7672b0facdefbc95.tar.xz linux-24bf86ccf9f5563f7d288f8b7672b0facdefbc95.zip | |
drm/i915/dsi: Enable dithering for 6 bpc panels
The display engine has 2 dithering enable bits which both need to be set
for dithering to happen, 1 in the PIPECONF register which is taken care of
by i9xx_set_pipeconf() and a second bit at the encoder level.
The dsi code was not setting the encoder level dithering enable bit causing
dithering to be disabled, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181201113148.23184-2-hdegoede@redhat.com
| -rw-r--r-- | drivers/gpu/drm/i915/vlv_dsi.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c index 54cbd8eb1718..4d47910e5184 100644 --- a/drivers/gpu/drm/i915/vlv_dsi.c +++ b/drivers/gpu/drm/i915/vlv_dsi.c @@ -678,6 +678,10 @@ static void intel_dsi_port_enable(struct intel_encoder *encoder, LANE_CONFIGURATION_DUAL_LINK_B : LANE_CONFIGURATION_DUAL_LINK_A; } + + if (intel_dsi->pixel_format != MIPI_DSI_FMT_RGB888) + temp |= DITHERING_ENABLE; + /* assert ip_tg_enable signal */ I915_WRITE(port_ctrl, temp | DPI_ENABLE); POSTING_READ(port_ctrl); |