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authorTony Lindgren <tony@atomide.com>2012-05-09 01:31:13 +0200
committerTony Lindgren <tony@atomide.com>2012-05-09 19:27:35 +0200
commit256a4bd79632413b691fc7bc6c1dadf92494bb01 (patch)
tree1e4ed55619f98d2d6a8ecf67d754489529ab0ec1
parentARM: OMAP: fix trivial warnings for dspbridge (diff)
downloadlinux-256a4bd79632413b691fc7bc6c1dadf92494bb01.tar.xz
linux-256a4bd79632413b691fc7bc6c1dadf92494bb01.zip
ARM: OMAP2+: Incorrect Register Offsets in OMAP Mailbox
Looks like the register offsets are incorrect in the OMAP mailbox code (arch/arm/mach-omap2/mailbox.c) for the OMAP4_MAILBOX_IRQ* macros. The discrepancy is with p.224 of TI document SPRUGX9 and p3891 of SWPU231K. Acked-by: Vaibhav Bedia <vaibhav.bedia@ti.com> Signed-off-by: Henry Chan <enli.chan@gmail.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r--arch/arm/mach-omap2/mailbox.c6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/mailbox.c b/arch/arm/mach-omap2/mailbox.c
index 415a6f1cf419..19b8b6774862 100644
--- a/arch/arm/mach-omap2/mailbox.c
+++ b/arch/arm/mach-omap2/mailbox.c
@@ -26,9 +26,9 @@
#define MAILBOX_IRQSTATUS(u) (0x100 + 8 * (u))
#define MAILBOX_IRQENABLE(u) (0x104 + 8 * (u))
-#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 10 * (u))
-#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 10 * (u))
+#define OMAP4_MAILBOX_IRQSTATUS(u) (0x104 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE(u) (0x108 + 0x10 * (u))
+#define OMAP4_MAILBOX_IRQENABLE_CLR(u) (0x10c + 0x10 * (u))
#define MAILBOX_IRQ_NEWMSG(m) (1 << (2 * (m)))
#define MAILBOX_IRQ_NOTFULL(m) (1 << (2 * (m) + 1))