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| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2016-05-20 09:09:59 +0200 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2016-05-30 02:37:11 +0200 |
| commit | 34ea4b4a827b4ee76295501b7df61fc904ab8ae3 (patch) | |
| tree | 7bb4ea36d2bebda0fa8375eaea4aeb67be2be887 | |
| parent | ARM: dts: r8a7793: Fix W=1 dtc warnings (diff) | |
| download | linux-34ea4b4a827b4ee76295501b7df61fc904ab8ae3.tar.xz linux-34ea4b4a827b4ee76295501b7df61fc904ab8ae3.zip | |
ARM: dts: r8a7794: Fix W=1 dtc warnings
Warning (unit_address_vs_reg): Node /cache-controller@1 has a unit name, but no reg property
Move the cache-controller node under the cpus node, and make its unit
name and reg property match the MPIDR value.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
| -rw-r--r-- | arch/arm/boot/dts/r8a7794.dtsi | 13 |
1 files changed, 7 insertions, 6 deletions
diff --git a/arch/arm/boot/dts/r8a7794.dtsi b/arch/arm/boot/dts/r8a7794.dtsi index ad1df8317575..685f986cf962 100644 --- a/arch/arm/boot/dts/r8a7794.dtsi +++ b/arch/arm/boot/dts/r8a7794.dtsi @@ -55,13 +55,14 @@ power-domains = <&sysc R8A7794_PD_CA7_CPU1>; next-level-cache = <&L2_CA7>; }; - }; - L2_CA7: cache-controller@1 { - compatible = "cache"; - power-domains = <&sysc R8A7794_PD_CA7_SCU>; - cache-unified; - cache-level = <2>; + L2_CA7: cache-controller@0 { + compatible = "cache"; + reg = <0>; + power-domains = <&sysc R8A7794_PD_CA7_SCU>; + cache-unified; + cache-level = <2>; + }; }; gic: interrupt-controller@f1001000 { |