diff options
| author | Anusha Srivatsa <anusha.srivatsa@intel.com> | 2018-10-31 01:19:17 +0100 |
|---|---|---|
| committer | Manasi Navare <manasi.d.navare@intel.com> | 2018-10-31 22:05:08 +0100 |
| commit | 35b876db4a425e58d7fe63eb363bbfa50b8e4e74 (patch) | |
| tree | 10cba1f39e2adf289b4946bda1ef82298a95c490 | |
| parent | drm/i915/icl: Program HS_TX_TIMEOUT/LP_RX_TIMEOUT/TA_TIMEOUT registers (diff) | |
| download | linux-35b876db4a425e58d7fe63eb363bbfa50b8e4e74.tar.xz linux-35b876db4a425e58d7fe63eb363bbfa50b8e4e74.zip | |
drm/i915/dsc: Add slice_row_per_frame in DSC PPS programming
Add the newly added slice_row_per_frame parameter
in the Picture Parameter Set registers.
This defines the number of vertically stacked slices
in a frame.
Credits to Manasi for noticing bSpec change.
Suggested-by: Manasi Navare <manasi.d.navare@intel.com>
Cc: Manasi Navare <manasi.d.navare@intel.com>
Signed-off-by: Anusha Srivatsa <anusha.srivatsa@intel.com>
Reviewed-by: Manasi Navare <manasi.d.navare@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20181031001923.31442-1-manasi.d.navare@intel.com
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 8d089ef848b2..55d32ca2051b 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -10977,6 +10977,7 @@ enum skl_power_gate { #define ICL_DSC1_PICTURE_PARAMETER_SET_16(pipe) _MMIO_PIPE((pipe) - PIPE_B, \ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PB, \ _ICL_DSC1_PICTURE_PARAMETER_SET_16_PC) +#define DSC_SLICE_ROW_PER_FRAME(slice_row_per_frame) ((slice_row_per_frame) << 20) #define DSC_SLICE_PER_LINE(slice_per_line) ((slice_per_line) << 16) #define DSC_SLICE_CHUNK_SIZE(slice_chunk_size) ((slice_chunk_size) << 0) |