diff options
| author | John Hsu <KCHSU0@nuvoton.com> | 2016-03-30 08:57:11 +0200 |
|---|---|---|
| committer | Mark Brown <broonie@kernel.org> | 2016-05-30 17:17:44 +0200 |
| commit | 3f039169ddc3edb2ecad03034843833d5b5a455f (patch) | |
| tree | c131f7974f639a6bc0fcd9d3dc4ab7c3add79e1d | |
| parent | ASoC: nau8825: change output power for interrupt (diff) | |
| download | linux-3f039169ddc3edb2ecad03034843833d5b5a455f.tar.xz linux-3f039169ddc3edb2ecad03034843833d5b5a455f.zip | |
ASoC: nau8825: assign DAC Ch to match headset L/R
The default value of DAC channel select is reverse in codec.
For normal usage, switch the channel select when codec bootup.
Signed-off-by: John Hsu <KCHSU0@nuvoton.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
| -rw-r--r-- | sound/soc/codecs/nau8825.c | 5 | ||||
| -rw-r--r-- | sound/soc/codecs/nau8825.h | 6 |
2 files changed, 11 insertions, 0 deletions
diff --git a/sound/soc/codecs/nau8825.c b/sound/soc/codecs/nau8825.c index 3eb76c5526dc..81fc97b07751 100644 --- a/sound/soc/codecs/nau8825.c +++ b/sound/soc/codecs/nau8825.c @@ -946,6 +946,11 @@ static void nau8825_init_regs(struct nau8825 *nau8825) NAU8825_RDAC_CLK_DELAY_MASK | NAU8825_RDAC_VREF_MASK, (0x2 << NAU8825_RDAC_CLK_DELAY_SFT) | (0x3 << NAU8825_RDAC_VREF_SFT)); + /* Config L/R channel */ + regmap_update_bits(nau8825->regmap, NAU8825_REG_DACL_CTRL, + NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_L); + regmap_update_bits(nau8825->regmap, NAU8825_REG_DACR_CTRL, + NAU8825_DACL_CH_SEL_MASK, NAU8825_DACL_CH_SEL_R); } static const struct regmap_config nau8825_regmap_config = { diff --git a/sound/soc/codecs/nau8825.h b/sound/soc/codecs/nau8825.h index 4427df99de24..9e6cb6262bf2 100644 --- a/sound/soc/codecs/nau8825.h +++ b/sound/soc/codecs/nau8825.h @@ -257,9 +257,15 @@ /* DACL_CTRL (0x33) */ #define NAU8825_DACL_CH_SEL_SFT 9 +#define NAU8825_DACL_CH_SEL_MASK (0x1 << NAU8825_DACL_CH_SEL_SFT) +#define NAU8825_DACL_CH_SEL_L (0x0 << NAU8825_DACL_CH_SEL_SFT) +#define NAU8825_DACL_CH_SEL_R (0x1 << NAU8825_DACL_CH_SEL_SFT) /* DACR_CTRL (0x34) */ #define NAU8825_DACR_CH_SEL_SFT 9 +#define NAU8825_DACR_CH_SEL_MASK (0x1 << NAU8825_DACR_CH_SEL_SFT) +#define NAU8825_DACR_CH_SEL_L (0x0 << NAU8825_DACR_CH_SEL_SFT) +#define NAU8825_DACR_CH_SEL_R (0x1 << NAU8825_DACR_CH_SEL_SFT) /* CLASSG_CTRL (0x50) */ #define NAU8825_CLASSG_TIMER_SFT 8 |