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| author | Leo Yan <leo.yan@linaro.org> | 2021-08-09 13:14:02 +0200 |
|---|---|---|
| committer | Peter Zijlstra <peterz@infradead.org> | 2021-09-17 15:08:38 +0200 |
| commit | 41100833cdd8b1bef363b81a6482d74711c116ad (patch) | |
| tree | 9893aeb221c1e071aa92f9ca582b468f69068e98 | |
| parent | perf/x86/intel/uncore: Fix Intel SPR M3UPI event constraints (diff) | |
| download | linux-41100833cdd8b1bef363b81a6482d74711c116ad.tar.xz linux-41100833cdd8b1bef363b81a6482d74711c116ad.zip | |
perf/x86: Add compiler barrier after updating BTS
Since BTS is coherent, simply add a compiler barrier to separate the BTS
update and aux_head store.
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lkml.kernel.org/r/20210809111407.596077-5-leo.yan@linaro.org
| -rw-r--r-- | arch/x86/events/intel/bts.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/events/intel/bts.c b/arch/x86/events/intel/bts.c index 6320d2cfd9d3..974e917e65b2 100644 --- a/arch/x86/events/intel/bts.c +++ b/arch/x86/events/intel/bts.c @@ -209,6 +209,12 @@ static void bts_update(struct bts_ctx *bts) } else { local_set(&buf->data_size, head); } + + /* + * Since BTS is coherent, just add compiler barrier to ensure + * BTS updating is ordered against bts::handle::event. + */ + barrier(); } static int |