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| author | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 14:47:25 +0100 |
|---|---|---|
| committer | Arnd Bergmann <arnd@arndb.de> | 2019-02-15 14:48:00 +0100 |
| commit | 55b97be83f2c0a8327d05e74482b3c3d25719ca6 (patch) | |
| tree | 72b28161abef8de10cd552571e815671d980d8ba | |
| parent | Merge tag 'v5.1-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kerne... (diff) | |
| parent | ARM: dts: stm32: Enable thermal sensor support on STM32MP157c-ed1 (diff) | |
| download | linux-55b97be83f2c0a8327d05e74482b3c3d25719ca6.tar.xz linux-55b97be83f2c0a8327d05e74482b3c3d25719ca6.zip | |
Merge tag 'stm32-dt-for-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32 into arm/dt
STM32 DT updates for v5.1, round 1
Highlights:
----------
MPU part:
-Enable Digital Thermal Sensor (dts) on stm32mp157c-ed1 (and so ev1).
MCU part:
-Add SPI support on stm32f429 SOC (4 SPIs instances).
* tag 'stm32-dt-for-v5.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/atorgue/stm32:
ARM: dts: stm32: Enable thermal sensor support on STM32MP157c-ed1
ARM: dts: stm32: add SPI support on STM32F429 SoC
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
| -rw-r--r-- | arch/arm/boot/dts/stm32f429.dtsi | 60 | ||||
| -rw-r--r-- | arch/arm/boot/dts/stm32mp157c-ed1.dts | 4 |
2 files changed, 64 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/stm32f429.dtsi b/arch/arm/boot/dts/stm32f429.dtsi index c29aa9d2f6d3..588b6ef94e93 100644 --- a/arch/arm/boot/dts/stm32f429.dtsi +++ b/arch/arm/boot/dts/stm32f429.dtsi @@ -316,6 +316,26 @@ status = "disabled"; }; + spi2: spi@40003800 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003800 0x400>; + interrupts = <36>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI2)>; + status = "disabled"; + }; + + spi3: spi@40003c00 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40003c00 0x400>; + interrupts = <51>; + clocks = <&rcc 0 STM32F4_APB1_CLOCK(SPI3)>; + status = "disabled"; + }; + usart2: serial@40004400 { compatible = "st,stm32-uart"; reg = <0x40004400 0x400>; @@ -525,6 +545,26 @@ status = "disabled"; }; + spi1: spi@40013000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013000 0x400>; + interrupts = <35>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI1)>; + status = "disabled"; + }; + + spi4: spi@40013400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40013400 0x400>; + interrupts = <84>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI4)>; + status = "disabled"; + }; + syscfg: system-config@40013800 { compatible = "syscon"; reg = <0x40013800 0x400>; @@ -589,6 +629,26 @@ }; }; + spi5: spi@40015000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015000 0x400>; + interrupts = <85>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI5)>; + status = "disabled"; + }; + + spi6: spi@40015400 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32f4-spi"; + reg = <0x40015400 0x400>; + interrupts = <86>; + clocks = <&rcc 0 STM32F4_APB2_CLOCK(SPI6)>; + status = "disabled"; + }; + pwrcfg: power-config@40007000 { compatible = "syscon"; reg = <0x40007000 0x400>; diff --git a/arch/arm/boot/dts/stm32mp157c-ed1.dts b/arch/arm/boot/dts/stm32mp157c-ed1.dts index 2890204680ba..d66edb0c66cd 100644 --- a/arch/arm/boot/dts/stm32mp157c-ed1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ed1.dts @@ -50,6 +50,10 @@ }; }; +&dts { + status = "okay"; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; |