diff options
| author | Thierry Reding <treding@nvidia.com> | 2019-07-24 15:47:54 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2019-10-29 20:29:14 +0100 |
| commit | 5d089d42bc36d54f459fdfb5caf0fe9f3b14ae09 (patch) | |
| tree | ad56fd399eb26c03a6ad1195759b9307a5c8f12c | |
| parent | ARM: tegra: Add stmpe-adc DT node to Toradex T30 modules (diff) | |
| download | linux-5d089d42bc36d54f459fdfb5caf0fe9f3b14ae09.tar.xz linux-5d089d42bc36d54f459fdfb5caf0fe9f3b14ae09.zip | |
ARM: tegra: Add SOR0_OUT clock on Tegra124
This clock is needed for eDP to properly function, so add it to the SOR
device tree node.
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index b113e47b2b2a..413bfb981de8 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -157,10 +157,11 @@ reg = <0x0 0x54540000 0x0 0x00040000>; interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; clocks = <&tegra_car TEGRA124_CLK_SOR0>, + <&tegra_car TEGRA124_CLK_SOR0_OUT>, <&tegra_car TEGRA124_CLK_PLL_D_OUT0>, <&tegra_car TEGRA124_CLK_PLL_DP>, <&tegra_car TEGRA124_CLK_CLK_M>; - clock-names = "sor", "parent", "dp", "safe"; + clock-names = "sor", "out", "parent", "dp", "safe"; resets = <&tegra_car 182>; reset-names = "sor"; status = "disabled"; |