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| author | Radim Krčmář <rkrcmar@redhat.com> | 2017-10-06 19:25:54 +0200 |
|---|---|---|
| committer | Paolo Bonzini <pbonzini@redhat.com> | 2017-10-12 14:01:54 +0200 |
| commit | 5d74a6999368ad1991491b1913bb80faf1925e67 (patch) | |
| tree | 11d7b1be0a3810b03ecf7dd66374194194239255 | |
| parent | KVM: x86: handle 0 write to TSC_DEADLINE MSR (diff) | |
| download | linux-5d74a6999368ad1991491b1913bb80faf1925e67.tar.xz linux-5d74a6999368ad1991491b1913bb80faf1925e67.zip | |
KVM: x86: really disarm lapic timer when clearing TMICT
preemption timer only looks at tscdeadline and could inject already
disarmed timer.
Signed-off-by: Radim Krčmář <rkrcmar@redhat.com>
Reviewed-by: Wanpeng Li <wanpeng.li@hotmail.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
| -rw-r--r-- | arch/x86/kvm/lapic.c | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c index 39c1ae11ce1d..96ade848ae0b 100644 --- a/arch/x86/kvm/lapic.c +++ b/arch/x86/kvm/lapic.c @@ -1489,8 +1489,10 @@ static bool set_target_expiration(struct kvm_lapic *apic) apic->lapic_timer.period = (u64)kvm_lapic_get_reg(apic, APIC_TMICT) * APIC_BUS_CYCLE_NS * apic->divide_count; - if (!apic->lapic_timer.period) + if (!apic->lapic_timer.period) { + apic->lapic_timer.tscdeadline = 0; return false; + } limit_periodic_timer_frequency(apic); |