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| author | Will Deacon <will.deacon@arm.com> | 2015-12-22 15:45:35 +0100 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-12-22 15:45:35 +0100 |
| commit | 5d7ee87708d4d86fcc32afc9552d05f7625d303d (patch) | |
| tree | 4cc31e70c9716774c2cb6cf45413aec67d658a35 | |
| parent | arm64: perf: add format entry to describe event -> config mapping (diff) | |
| download | linux-5d7ee87708d4d86fcc32afc9552d05f7625d303d.tar.xz linux-5d7ee87708d4d86fcc32afc9552d05f7625d303d.zip | |
arm64: perf: add support for Cortex-A72
Cortex-A72 has a PMUv3 implementation that is compatible with the PMU
implemented by Cortex-A57.
This patch hooks up the new compatible string so that the Cortex-A57
event mappings are used.
Signed-off-by: Will Deacon <will.deacon@arm.com>
| -rw-r--r-- | Documentation/devicetree/bindings/arm/pmu.txt | 1 | ||||
| -rw-r--r-- | arch/arm64/kernel/perf_event.c | 13 |
2 files changed, 13 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/arm/pmu.txt b/Documentation/devicetree/bindings/arm/pmu.txt index a6cd14888bed..56518839f52a 100644 --- a/Documentation/devicetree/bindings/arm/pmu.txt +++ b/Documentation/devicetree/bindings/arm/pmu.txt @@ -9,6 +9,7 @@ Required properties: - compatible : should be one of "apm,potenza-pmu" "arm,armv8-pmuv3" + "arm,cortex-a72-pmu" "arm,cortex-a57-pmu" "arm,cortex-a53-pmu" "arm,cortex-a17-pmu" diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c index 6fdcfb671309..f7ab14c4d5df 100644 --- a/arch/arm64/kernel/perf_event.c +++ b/arch/arm64/kernel/perf_event.c @@ -90,7 +90,7 @@ /* ARMv8 Cortex-A53 specific event types. */ #define ARMV8_A53_PERFCTR_PREFETCH_LINEFILL 0xC2 -/* ARMv8 Cortex-A57 specific event types. */ +/* ARMv8 Cortex-A57 and Cortex-A72 specific event types. */ #define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_LD 0x40 #define ARMV8_A57_PERFCTR_L1_DCACHE_ACCESS_ST 0x41 #define ARMV8_A57_PERFCTR_L1_DCACHE_REFILL_LD 0x42 @@ -120,6 +120,7 @@ static const unsigned armv8_a53_perf_map[PERF_COUNT_HW_MAX] = { [PERF_COUNT_HW_BUS_CYCLES] = ARMV8_PMUV3_PERFCTR_BUS_CYCLES, }; +/* ARM Cortex-A57 and Cortex-A72 events mapping. */ static const unsigned armv8_a57_perf_map[PERF_COUNT_HW_MAX] = { PERF_MAP_ALL_UNSUPPORTED, [PERF_COUNT_HW_CPU_CYCLES] = ARMV8_PMUV3_PERFCTR_CLOCK_CYCLES, @@ -801,10 +802,20 @@ static int armv8_a57_pmu_init(struct arm_pmu *cpu_pmu) return armv8pmu_probe_num_events(cpu_pmu); } +static int armv8_a72_pmu_init(struct arm_pmu *cpu_pmu) +{ + armv8_pmu_init(cpu_pmu); + cpu_pmu->name = "armv8_cortex_a72"; + cpu_pmu->map_event = armv8_a57_map_event; + cpu_pmu->pmu.attr_groups = armv8_pmuv3_attr_groups; + return armv8pmu_probe_num_events(cpu_pmu); +} + static const struct of_device_id armv8_pmu_of_device_ids[] = { {.compatible = "arm,armv8-pmuv3", .data = armv8_pmuv3_init}, {.compatible = "arm,cortex-a53-pmu", .data = armv8_a53_pmu_init}, {.compatible = "arm,cortex-a57-pmu", .data = armv8_a57_pmu_init}, + {.compatible = "arm,cortex-a72-pmu", .data = armv8_a72_pmu_init}, {}, }; |