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authorXiong Zhang <xiong.y.zhang@intel.com>2019-05-27 07:45:50 +0200
committerZhenyu Wang <zhenyuw@linux.intel.com>2019-05-30 05:31:43 +0200
commit5e0b3f3b27731f660612249b74b520f1bce6c198 (patch)
tree393b1520dfb99cd38870ba5440682355034496c7
parentdrm/i915/gvt: Fix vGPU CSFE_CHICKEN1_REG mmio handler (diff)
downloadlinux-5e0b3f3b27731f660612249b74b520f1bce6c198.tar.xz
linux-5e0b3f3b27731f660612249b74b520f1bce6c198.zip
drm/i915/gvt: refine ggtt range validation
The vgpu ggtt range should be in vgpu aperture or hidden range. This patch enforce begin and end address check and guarantee both of them are in the valid range. For size=0, it will regress to vgpu_gmadr_is_valid(), will refine this usage in a later fix. Fixes: 2707e4446688 ("drm/i915/gvt: vGPU graphics memory virtualization") Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Xiong Zhang <xiong.y.zhang@intel.com> Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
-rw-r--r--drivers/gpu/drm/i915/gvt/gtt.c20
1 files changed, 13 insertions, 7 deletions
diff --git a/drivers/gpu/drm/i915/gvt/gtt.c b/drivers/gpu/drm/i915/gvt/gtt.c
index f3a75bb9ec27..d767c45a57e2 100644
--- a/drivers/gpu/drm/i915/gvt/gtt.c
+++ b/drivers/gpu/drm/i915/gvt/gtt.c
@@ -53,13 +53,19 @@ static int preallocated_oos_pages = 8192;
*/
bool intel_gvt_ggtt_validate_range(struct intel_vgpu *vgpu, u64 addr, u32 size)
{
- if ((!vgpu_gmadr_is_valid(vgpu, addr)) || (size
- && !vgpu_gmadr_is_valid(vgpu, addr + size - 1))) {
- gvt_vgpu_err("invalid range gmadr 0x%llx size 0x%x\n",
- addr, size);
- return false;
- }
- return true;
+ if (size == 0)
+ return vgpu_gmadr_is_valid(vgpu, addr);
+
+ if (vgpu_gmadr_is_aperture(vgpu, addr) &&
+ vgpu_gmadr_is_aperture(vgpu, addr + size - 1))
+ return true;
+ else if (vgpu_gmadr_is_hidden(vgpu, addr) &&
+ vgpu_gmadr_is_hidden(vgpu, addr + size - 1))
+ return true;
+
+ gvt_dbg_mm("Invalid ggtt range at 0x%llx, size: 0x%x\n",
+ addr, size);
+ return false;
}
/* translate a guest gmadr to host gmadr */