diff options
| author | Konrad Dybcio <konrad.dybcio@linaro.org> | 2023-04-14 13:06:36 +0200 |
|---|---|---|
| committer | Bjorn Andersson <andersson@kernel.org> | 2023-05-26 22:26:03 +0200 |
| commit | 63d56adf04b5795e54440dc5b7afddecb2966863 (patch) | |
| tree | 631573a0d3ebd31c16151eb31383aebd78b7d20d | |
| parent | clk: qcom: dispcc-qcm2290: Fix BI_TCXO_AO handling (diff) | |
| download | linux-63d56adf04b5795e54440dc5b7afddecb2966863.tar.xz linux-63d56adf04b5795e54440dc5b7afddecb2966863.zip | |
clk: qcom: dispcc-qcm2290: Fix GPLL0_OUT_DIV handling
GPLL0_OUT_DIV (.fw_name = "gcc_disp_gpll0_div_clk_src") was previously
made to reuse the same parent enum entry as GPLL0_OUT_MAIN
(.fw_name = "gcc_disp_gpll0_clk_src") in parent_map_2.
Resolve it by introducing its own entry in the parent enum and
correctly assigning it in disp_cc_parent_map_2[].
Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v2-2-bce7dd512fe4@linaro.org
| -rw-r--r-- | drivers/clk/qcom/dispcc-qcm2290.c | 7 |
1 files changed, 4 insertions, 3 deletions
diff --git a/drivers/clk/qcom/dispcc-qcm2290.c b/drivers/clk/qcom/dispcc-qcm2290.c index ee62aca4e5bb..44dd5cfcc150 100644 --- a/drivers/clk/qcom/dispcc-qcm2290.c +++ b/drivers/clk/qcom/dispcc-qcm2290.c @@ -28,6 +28,7 @@ enum { P_DISP_CC_PLL0_OUT_MAIN, P_DSI0_PHY_PLL_OUT_BYTECLK, P_DSI0_PHY_PLL_OUT_DSICLK, + P_GPLL0_OUT_DIV, P_GPLL0_OUT_MAIN, P_SLEEP_CLK, }; @@ -84,7 +85,7 @@ static const struct clk_parent_data disp_cc_parent_data_1[] = { static const struct parent_map disp_cc_parent_map_2[] = { { P_BI_TCXO_AO, 0 }, - { P_GPLL0_OUT_MAIN, 4 }, + { P_GPLL0_OUT_DIV, 4 }, }; static const struct clk_parent_data disp_cc_parent_data_2[] = { @@ -153,8 +154,8 @@ static struct clk_regmap_div disp_cc_mdss_byte0_div_clk_src = { static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = { F(19200000, P_BI_TCXO_AO, 1, 0, 0), - F(37500000, P_GPLL0_OUT_MAIN, 8, 0, 0), - F(75000000, P_GPLL0_OUT_MAIN, 4, 0, 0), + F(37500000, P_GPLL0_OUT_DIV, 8, 0, 0), + F(75000000, P_GPLL0_OUT_DIV, 4, 0, 0), { } }; |