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author | Felipe Balbi <balbi@ti.com> | 2014-09-15 23:15:09 +0200 |
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committer | Tony Lindgren <tony@atomide.com> | 2014-09-16 23:45:01 +0200 |
commit | 64d5947b9ee1284b38b8e212e7c94024452b2bb4 (patch) | |
tree | acb818559710e5d7e9260c930a72edbc753ca958 | |
parent | irqchip: omap-intc: correct maximum number or MIR registers (diff) | |
download | linux-64d5947b9ee1284b38b8e212e7c94024452b2bb4.tar.xz linux-64d5947b9ee1284b38b8e212e7c94024452b2bb4.zip |
irqchip: omap-intc: remove unnecessary comments
no fuctional changes.
Acked-by: Jason Cooper <jason@lakedaemon.net>
Signed-off-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
-rw-r--r-- | drivers/irqchip/irq-omap-intc.c | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/drivers/irqchip/irq-omap-intc.c b/drivers/irqchip/irq-omap-intc.c index 976d4c15fefd..f3814e79192d 100644 --- a/drivers/irqchip/irq-omap-intc.c +++ b/drivers/irqchip/irq-omap-intc.c @@ -56,14 +56,6 @@ #define INTC_PROTECTION_ENABLE (1 << 0) -/* - * OMAP2 has a number of different interrupt controllers, each interrupt - * controller is identified as its own "bank". Register definitions are - * fairly consistent for each bank, but not all registers are implemented - * for each bank.. when in doubt, consult the TRM. - */ - -/* Structure to save interrupt controller context */ struct omap_intc_regs { u32 sysconfig; u32 protection; @@ -79,7 +71,6 @@ static void __iomem *omap_irq_base; static int omap_nr_pending = 3; static int omap_nr_irqs = 96; -/* INTC bank register get/set */ static void intc_writel(u32 reg, u32 val) { writel_relaxed(val, omap_irq_base + reg); |