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| author | Russ Anderson <rja@sgi.com> | 2006-10-26 18:53:17 +0200 |
|---|---|---|
| committer | Tony Luck <tony.luck@intel.com> | 2006-12-07 20:02:53 +0100 |
| commit | 6533bdedac9ae2049ae77ebd7c28c65af3619de0 (patch) | |
| tree | 03ec755db1d5bf0589e9c9382b5dd1fb6ce6ed9a | |
| parent | [IA64] Add dp bit to cache and bus check structs (diff) | |
| download | linux-6533bdedac9ae2049ae77ebd7c28c65af3619de0.tar.xz linux-6533bdedac9ae2049ae77ebd7c28c65af3619de0.zip | |
[IA64] Add se bit to Processor State Parameter structure
Rev 2.2 of Volume 2 of "Intel Itanium Architecture Software Developer's
Manual" (January 2006) adds a se bit to the Processor State Parameter
fields (pages 2:299). This patch gets the structs back in sync
with the spec.
Signed-off-by: Russ Anderson (rja@sgi.com)
Signed-off-by: Tony Luck <tony.luck@intel.com>
| -rw-r--r-- | include/asm-ia64/pal.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h index b6d4f6f0c3c8..7423b10e8935 100644 --- a/include/asm-ia64/pal.h +++ b/include/asm-ia64/pal.h @@ -456,7 +456,9 @@ typedef struct pal_process_state_info_s { * by the processor */ - reserved2 : 11, + se : 1, /* Shared error. MCA in a + shared structure */ + reserved2 : 10, cc : 1, /* Cache check */ tc : 1, /* TLB check */ bc : 1, /* Bus check */ |