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| author | Daniel Palmer <daniel@0x0f.com> | 2021-02-23 07:18:27 +0100 |
|---|---|---|
| committer | Romain Perier <romain.perier@gmail.com> | 2022-02-16 19:21:01 +0100 |
| commit | 79f700c24b1314e3b49b9d998c38a56779ddbeba (patch) | |
| tree | 4459d28d85bdc2263e7bf36575406a00abb2cb34 | |
| parent | ARM: mstar: Link cpupll to cpu (diff) | |
| download | linux-79f700c24b1314e3b49b9d998c38a56779ddbeba.tar.xz linux-79f700c24b1314e3b49b9d998c38a56779ddbeba.zip | |
ARM: mstar: Link cpupll to second core
The second core also sources it's clock from the CPU PLL.
Signed-off-by: Daniel Palmer <daniel@0x0f.com>
Reviewed-by: Romain Perier <romain.perier@gmail.com>
| -rw-r--r-- | arch/arm/boot/dts/mstar-infinity2m.dtsi | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/mstar-infinity2m.dtsi b/arch/arm/boot/dts/mstar-infinity2m.dtsi index 6d4d1d224e96..dc339cd29778 100644 --- a/arch/arm/boot/dts/mstar-infinity2m.dtsi +++ b/arch/arm/boot/dts/mstar-infinity2m.dtsi @@ -11,6 +11,8 @@ device_type = "cpu"; compatible = "arm,cortex-a7"; reg = <0x1>; + clocks = <&cpupll>; + clock-names = "cpuclk"; }; }; |