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author | Vidya Sagar <vidyas@nvidia.com> | 2019-08-13 13:36:23 +0200 |
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committer | Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> | 2019-08-13 17:00:58 +0200 |
commit | 7b31a72e7195aebd620d504f28b97ad8398e95ec (patch) | |
tree | acce796209c682490c637fdc9245a2d869cdc49f | |
parent | PCI: dwc: Add support to enable CDM register check (diff) | |
download | linux-7b31a72e7195aebd620d504f28b97ad8398e95ec.tar.xz linux-7b31a72e7195aebd620d504f28b97ad8398e95ec.zip |
dt-bindings: Add PCIe supports-clkreq property
Some host controllers need to know the existence of clkreq signal routing
to downstream devices to be able to advertise low power features like
ASPM L1 substates. Without clkreq signal routing being present, enabling
ASPM L1 substates might lead to downstream devices being disconnected
from the bus. Hence a new device tree property 'supports-clkreq' is added
to make such host controllers aware of clkreq signal routing to
downstream devices.
Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Reviewed-by: Thierry Reding <treding@nvidia.com>
-rw-r--r-- | Documentation/devicetree/bindings/pci/pci.txt | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/pci/pci.txt b/Documentation/devicetree/bindings/pci/pci.txt index 2a5d91024059..29bcbd88f457 100644 --- a/Documentation/devicetree/bindings/pci/pci.txt +++ b/Documentation/devicetree/bindings/pci/pci.txt @@ -27,6 +27,11 @@ driver implementation may support the following properties: - reset-gpios: If present this property specifies PERST# GPIO. Host drivers can parse the GPIO and apply fundamental reset to endpoints. +- supports-clkreq: + If present this property specifies that CLKREQ signal routing exists from + root port to downstream device and host bridge drivers can do programming + which depends on CLKREQ signal existence. For example, programming root port + not to advertise ASPM L1 Sub-States support if there is no CLKREQ signal. PCI-PCI Bridge properties ------------------------- |