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authorJiaxun Yang <jiaxun.yang@flygoat.com>2023-04-04 11:33:43 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2023-04-05 09:45:09 +0200
commit918d779569dafd81fce4257c552aa4205c918c4a (patch)
treeb3bdb2695300bd994eda271eccc477f503167fb4
parentMIPS: mips-cm: Check availability of config registers (diff)
downloadlinux-918d779569dafd81fce4257c552aa4205c918c4a.tar.xz
linux-918d779569dafd81fce4257c552aa4205c918c4a.zip
MIPS: Octeon: Opt-out 4k_cache feature
Octeon has a different cache interface with traditional R4K one, just opt-out this flag for octeon to avoid run R4K cache initialization code accidentally. Also remove ISA level assumption for 4k cache. Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
-rw-r--r--arch/mips/include/asm/cpu-features.h2
-rw-r--r--arch/mips/kernel/cpu-probe.c2
2 files changed, 3 insertions, 1 deletions
diff --git a/arch/mips/include/asm/cpu-features.h b/arch/mips/include/asm/cpu-features.h
index c0983130a44c..c613426b0bfc 100644
--- a/arch/mips/include/asm/cpu-features.h
+++ b/arch/mips/include/asm/cpu-features.h
@@ -118,7 +118,7 @@
#define cpu_has_3k_cache __isa_lt_and_opt(1, MIPS_CPU_3K_CACHE)
#endif
#ifndef cpu_has_4k_cache
-#define cpu_has_4k_cache __isa_ge_or_opt(1, MIPS_CPU_4K_CACHE)
+#define cpu_has_4k_cache __opt(MIPS_CPU_4K_CACHE)
#endif
#ifndef cpu_has_octeon_cache
#define cpu_has_octeon_cache 0
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 7ddf07f255f3..6d15a398d389 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1602,6 +1602,8 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
{
decode_configs(c);
+ /* Octeon has different cache interface */
+ c->options &= ~MIPS_CPU_4K_CACHE;
switch (c->processor_id & PRID_IMP_MASK) {
case PRID_IMP_CAVIUM_CN38XX:
case PRID_IMP_CAVIUM_CN31XX: