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| author | Heiko Stuebner <heiko@sntech.de> | 2016-07-01 01:49:53 +0200 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-07-01 01:49:53 +0200 |
| commit | 9daa46cc649b90c464757114310bcc4d05098f44 (patch) | |
| tree | 83d076415762192d2689a179544a43c342124849 | |
| parent | clk: rockchip: include rk3228 downstream muxes into fractional dividers (diff) | |
| parent | clk: rockchip: add clock-ids for rk3228 MAC clocks (diff) | |
| download | linux-9daa46cc649b90c464757114310bcc4d05098f44.tar.xz linux-9daa46cc649b90c464757114310bcc4d05098f44.zip | |
Merge branch 'v4.8-shared/clkids' into v4.8-clk/next
| -rw-r--r-- | include/dt-bindings/clock/rk3228-cru.h | 15 |
1 files changed, 15 insertions, 0 deletions
diff --git a/include/dt-bindings/clock/rk3228-cru.h b/include/dt-bindings/clock/rk3228-cru.h index 5d43ed9b05ad..b27e2b1a65e3 100644 --- a/include/dt-bindings/clock/rk3228-cru.h +++ b/include/dt-bindings/clock/rk3228-cru.h @@ -52,6 +52,15 @@ #define SCLK_EMMC_SAMPLE 121 #define SCLK_VOP 122 #define SCLK_HDMI_HDCP 123 +#define SCLK_MAC_SRC 124 +#define SCLK_MAC_EXTCLK 125 +#define SCLK_MAC 126 +#define SCLK_MAC_REFOUT 127 +#define SCLK_MAC_REF 128 +#define SCLK_MAC_RX 129 +#define SCLK_MAC_TX 130 +#define SCLK_MAC_PHY 131 +#define SCLK_MAC_OUT 132 /* dclk gates */ #define DCLK_VOP 190 @@ -61,6 +70,7 @@ #define ACLK_DMAC 194 #define ACLK_PERI 210 #define ACLK_VOP 211 +#define ACLK_GMAC 212 /* pclk gates */ #define PCLK_GPIO0 320 @@ -82,8 +92,13 @@ #define PCLK_PERI 363 #define PCLK_HDMI_CTRL 364 #define PCLK_HDMI_PHY 365 +#define PCLK_GMAC 367 /* hclk gates */ +#define HCLK_I2S0_8CH 442 +#define HCLK_I2S1_8CH 443 +#define HCLK_I2S2_2CH 444 +#define HCLK_SPDIF_8CH 445 #define HCLK_VOP 452 #define HCLK_NANDC 453 #define HCLK_SDMMC 456 |