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authorArd Biesheuvel <ard.biesheuvel@linaro.org>2016-08-31 13:05:14 +0200
committerWill Deacon <will.deacon@arm.com>2016-09-02 12:47:51 +0200
commit9dcf7914ae238619ae019dcf82a91c817ff8628e (patch)
tree467135c4d1457e1e3cd95dbe338aee8dd06c81a1
parentarm64: head.S: move KASLR processing out of __enable_mmu() (diff)
downloadlinux-9dcf7914ae238619ae019dcf82a91c817ff8628e.tar.xz
linux-9dcf7914ae238619ae019dcf82a91c817ff8628e.zip
arm64: kernel: use x30 for __enable_mmu return address
Using x27 for passing to __enable_mmu what is essentially the return address makes the code look more complicated than it needs to be. So switch to x30/lr, and update the secondary and cpu_resume call sites to simply call __enable_mmu as an ordinary function, with a bl instruction. This requires the callers to be covered by .idmap.text. Reviewed-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
-rw-r--r--arch/arm64/kernel/head.S21
-rw-r--r--arch/arm64/kernel/sleep.S8
2 files changed, 9 insertions, 20 deletions
diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S
index 5543068da3ae..45b865e022cc 100644
--- a/arch/arm64/kernel/head.S
+++ b/arch/arm64/kernel/head.S
@@ -675,9 +675,9 @@ secondary_startup:
* Common entry point for secondary CPUs.
*/
bl __cpu_setup // initialise processor
-
- adr_l x27, __secondary_switch // address to jump to after enabling the MMU
- b __enable_mmu
+ bl __enable_mmu
+ ldr x8, =__secondary_switched
+ br x8
ENDPROC(secondary_startup)
__secondary_switched:
@@ -716,9 +716,9 @@ ENDPROC(__secondary_switched)
* Enable the MMU.
*
* x0 = SCTLR_EL1 value for turning on the MMU.
- * x27 = *virtual* address to jump to upon completion
*
- * Other registers depend on the function called upon completion.
+ * Returns to the caller via x30/lr. This requires the caller to be covered
+ * by the .idmap.text section.
*
* Checks if the selected granule size is supported by the CPU.
* If it isn't, park the CPU
@@ -744,7 +744,7 @@ ENTRY(__enable_mmu)
ic iallu
dsb nsh
isb
- br x27
+ ret
ENDPROC(__enable_mmu)
__no_granule_support:
@@ -789,9 +789,7 @@ __primary_switch:
mrs x20, sctlr_el1 // preserve old SCTLR_EL1 value
#endif
- adr x27, 0f
- b __enable_mmu
-0:
+ bl __enable_mmu
#ifdef CONFIG_RELOCATABLE
bl __relocate_kernel
#ifdef CONFIG_RANDOMIZE_BASE
@@ -822,8 +820,3 @@ __primary_switch:
ldr x8, =__primary_switched
br x8
ENDPROC(__primary_switch)
-
-__secondary_switch:
- ldr x8, =__secondary_switched
- br x8
-ENDPROC(__secondary_switch)
diff --git a/arch/arm64/kernel/sleep.S b/arch/arm64/kernel/sleep.S
index 6adc76bf8f91..0f7e0b2ac64c 100644
--- a/arch/arm64/kernel/sleep.S
+++ b/arch/arm64/kernel/sleep.S
@@ -100,14 +100,10 @@ ENTRY(cpu_resume)
bl el2_setup // if in EL2 drop to EL1 cleanly
bl __cpu_setup
/* enable the MMU early - so we can access sleep_save_stash by va */
- adr_l x27, _resume_switched /* __enable_mmu will branch here */
- b __enable_mmu
-ENDPROC(cpu_resume)
-
-_resume_switched:
+ bl __enable_mmu
ldr x8, =_cpu_resume
br x8
-ENDPROC(_resume_switched)
+ENDPROC(cpu_resume)
.ltorg
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