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authorJiaxun Yang <jiaxun.yang@flygoat.com>2024-06-12 10:54:28 +0200
committerThomas Bogendoerfer <tsbogend@alpha.franken.de>2024-07-03 16:44:49 +0200
commitc171186c177970d3ec22dd814f2693f1f7fc1e7d (patch)
tree242fc8438c003e9a5358c607ea963d538f97600e
parentmips: bmips: enable RAC on BMIPS4350 (diff)
downloadlinux-c171186c177970d3ec22dd814f2693f1f7fc1e7d.tar.xz
linux-c171186c177970d3ec22dd814f2693f1f7fc1e7d.zip
MIPS: csrc-r4k: Refine rating computation
Increase frequency addend dividend to 10000000 (10MHz) to reasonably accommodate multi GHz level mips_hpt_frequency. Cap rating of csrc-r4k into 299 to ensure it doesn't go into "Desired" range, given all the drama we have with CP0 count registers (SMP sync, behaviour on wait etc). Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
-rw-r--r--arch/mips/kernel/csrc-r4k.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index edc4afc080fa..f02ae333f4f9 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -111,7 +111,8 @@ int __init init_r4k_clocksource(void)
return -ENXIO;
/* Calculate a somewhat reasonable rating value */
- clocksource_mips.rating = 200 + mips_hpt_frequency / 10000000;
+ clocksource_mips.rating = 200;
+ clocksource_mips.rating += clamp(mips_hpt_frequency / 10000000, 0, 99);
/*
* R2 onwards makes the count accessible to user mode so it can be used