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| author | Dmitry Osipenko <digetx@gmail.com> | 2017-10-04 01:02:41 +0200 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2017-11-01 15:00:05 +0100 |
| commit | d80a32fe98b7ce428669b774c3d10ecae3bc6e6d (patch) | |
| tree | 03e39fd10340e1a04c7be43a91b0098bf7a30c51 | |
| parent | clk: tegra: Use common definition of APBDMA clock gate (diff) | |
| download | linux-d80a32fe98b7ce428669b774c3d10ecae3bc6e6d.tar.xz linux-d80a32fe98b7ce428669b774c3d10ecae3bc6e6d.zip | |
clk: tegra: Bump SCLK clock rate to 216 MHz
AHB DMA is a running on 1/2 of SCLK rate, APB DMA on 1/4. Increasing SCLK
rate results in an increased DMA transfer rate.
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | drivers/clk/tegra/clk-tegra20.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/tegra/clk-tegra20.c b/drivers/clk/tegra/clk-tegra20.c index 57a1387ea992..cbd5a2e5c569 100644 --- a/drivers/clk/tegra/clk-tegra20.c +++ b/drivers/clk/tegra/clk-tegra20.c @@ -1020,7 +1020,7 @@ static struct tegra_clk_init_table init_table[] __initdata = { { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 }, { TEGRA20_CLK_PLL_P_OUT4, TEGRA20_CLK_CLK_MAX, 24000000, 1 }, { TEGRA20_CLK_PLL_C, TEGRA20_CLK_CLK_MAX, 600000000, 1 }, - { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 120000000, 1 }, + { TEGRA20_CLK_PLL_C_OUT1, TEGRA20_CLK_CLK_MAX, 216000000, 1 }, { TEGRA20_CLK_SCLK, TEGRA20_CLK_PLL_C_OUT1, 0, 1 }, { TEGRA20_CLK_HCLK, TEGRA20_CLK_CLK_MAX, 0, 1 }, { TEGRA20_CLK_PCLK, TEGRA20_CLK_CLK_MAX, 60000000, 1 }, |