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| author | Inderpal Singh <inderpal.singh@linaro.org> | 2013-04-04 09:01:15 +0200 |
|---|---|---|
| committer | Kukjin Kim <kgene.kim@samsung.com> | 2013-04-04 09:01:20 +0200 |
| commit | d9cdeb814fd6bb1b5eaa49c5848f10ba7acf992a (patch) | |
| tree | 13704f870f16b8aed79cf0d186f4cfa0086436fe | |
| parent | ARM: S3C64XX: Slow down mic detection rate for wm5102 (diff) | |
| download | linux-d9cdeb814fd6bb1b5eaa49c5848f10ba7acf992a.tar.xz linux-d9cdeb814fd6bb1b5eaa49c5848f10ba7acf992a.zip | |
ARM: SAMSUNG: check processor type before cache restoration in resume
Only cortex-a9 based samsung platforms have l2x0 cache controller. Hence check
the same before restoring the cache in resume.
This is needed for single kernel image.
Signed-off-by: Inderpal Singh <inderpal.singh@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
| -rw-r--r-- | arch/arm/plat-samsung/s5p-sleep.S | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/plat-samsung/s5p-sleep.S b/arch/arm/plat-samsung/s5p-sleep.S index bdf6dadf8790..a030e7301da8 100644 --- a/arch/arm/plat-samsung/s5p-sleep.S +++ b/arch/arm/plat-samsung/s5p-sleep.S @@ -25,6 +25,9 @@ #include <asm/asm-offsets.h> #include <asm/hardware/cache-l2x0.h> +#define CPU_MASK 0xff0ffff0 +#define CPU_CORTEX_A9 0x410fc090 + /* * The following code is located into the .data section. This is to * allow l2x0_regs_phys to be accessed with a relative load while we @@ -51,6 +54,12 @@ ENTRY(s3c_cpu_resume) #ifdef CONFIG_CACHE_L2X0 + mrc p15, 0, r0, c0, c0, 0 + ldr r1, =CPU_MASK + and r0, r0, r1 + ldr r1, =CPU_CORTEX_A9 + cmp r0, r1 + bne resume_l2on adr r0, l2x0_regs_phys ldr r0, [r0] ldr r1, [r0, #L2X0_R_PHY_BASE] |