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| author | Sowjanya Komatineni <skomatineni@nvidia.com> | 2020-11-23 21:17:20 +0100 |
|---|---|---|
| committer | Thierry Reding <treding@nvidia.com> | 2020-11-26 19:06:47 +0100 |
| commit | dd2a21d0930b3f5b8d5643c8d41008f8f2557d73 (patch) | |
| tree | 8a4338178072ede6116f9e70bfb2ba9257785202 | |
| parent | ARM: tegra: Correct EMC registers size in Tegra20 device-tree (diff) | |
| download | linux-dd2a21d0930b3f5b8d5643c8d41008f8f2557d73.tar.xz linux-dd2a21d0930b3f5b8d5643c8d41008f8f2557d73.zip | |
ARM: tegra: Change order of SATA resets for Tegra124
Tegra AHCI dt-binding doc is converted from text based to yaml based.
dtbs_check valdiation strictly follows reset-names order specified
in yaml dt-binding.
Tegra124 thru Tegra210 has 3 resets sata, sata-oob and sata-cold.
Tegra186 has 2 resets sata and sata-cold.
This patch changes order of SATA resets to maintain proper resets
order for commonly available resets across Tegra124 thru Tegra186
for dtbs_check to pass.
Signed-off-by: Sowjanya Komatineni <skomatineni@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
| -rw-r--r-- | arch/arm/boot/dts/tegra124.dtsi | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/arm/boot/dts/tegra124.dtsi b/arch/arm/boot/dts/tegra124.dtsi index d7001b27c3e6..e61e68a0bb58 100644 --- a/arch/arm/boot/dts/tegra124.dtsi +++ b/arch/arm/boot/dts/tegra124.dtsi @@ -650,9 +650,9 @@ <&tegra_car TEGRA124_CLK_PLL_E>; clock-names = "sata", "sata-oob", "cml1", "pll_e"; resets = <&tegra_car 124>, - <&tegra_car 123>, - <&tegra_car 129>; - reset-names = "sata", "sata-oob", "sata-cold"; + <&tegra_car 129>, + <&tegra_car 123>; + reset-names = "sata", "sata-cold", "sata-oob"; status = "disabled"; }; |