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authorJonathan Marek <jonathan@marek.ca>2020-09-23 18:06:28 +0200
committerStephen Boyd <sboyd@kernel.org>2020-10-14 03:05:03 +0200
commitdf3f61d2cdc9eac4c9c8316ca2d1a2efea39c8a0 (patch)
tree562dd80a8869d69b48a0b832eab841c29b841650
parentdt-bindings: clock: combine qcom,sdm845-videocc and qcom,sc7180-videocc (diff)
downloadlinux-df3f61d2cdc9eac4c9c8316ca2d1a2efea39c8a0.tar.xz
linux-df3f61d2cdc9eac4c9c8316ca2d1a2efea39c8a0.zip
dt-bindings: clock: add SM8150 QCOM video clock bindings
Add device tree bindings for video clock controller for SM8150 SoCs. Signed-off-by: Jonathan Marek <jonathan@marek.ca> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20200923160635.28370-3-jonathan@marek.ca Signed-off-by: Stephen Boyd <sboyd@kernel.org>
-rw-r--r--Documentation/devicetree/bindings/clock/qcom,videocc.yaml4
-rw-r--r--include/dt-bindings/clock/qcom,videocc-sm8150.h25
2 files changed, 28 insertions, 1 deletions
diff --git a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
index 874be03c33f5..bb1c1a841b68 100644
--- a/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
+++ b/Documentation/devicetree/bindings/clock/qcom,videocc.yaml
@@ -11,17 +11,19 @@ maintainers:
description: |
Qualcomm video clock control module which supports the clocks, resets and
- power domains on SDM845/SC7180.
+ power domains on SDM845/SC7180/SM8150.
See also:
dt-bindings/clock/qcom,videocc-sc7180.h
dt-bindings/clock/qcom,videocc-sdm845.h
+ dt-bindings/clock/qcom,videocc-sm8150.h
properties:
compatible:
enum:
- qcom,sc7180-videocc
- qcom,sdm845-videocc
+ - qcom,sm8150-videocc
clocks:
items:
diff --git a/include/dt-bindings/clock/qcom,videocc-sm8150.h b/include/dt-bindings/clock/qcom,videocc-sm8150.h
new file mode 100644
index 000000000000..e24ee840cfdb
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,videocc-sm8150.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (c) 2017-2020, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H
+#define _DT_BINDINGS_CLK_QCOM_VIDEO_CC_SM8150_H
+
+/* VIDEO_CC clocks */
+#define VIDEO_CC_IRIS_AHB_CLK 0
+#define VIDEO_CC_IRIS_CLK_SRC 1
+#define VIDEO_CC_MVS0_CORE_CLK 2
+#define VIDEO_CC_MVS1_CORE_CLK 3
+#define VIDEO_CC_MVSC_CORE_CLK 4
+#define VIDEO_CC_PLL0 5
+
+/* VIDEO_CC Resets */
+#define VIDEO_CC_MVSC_CORE_CLK_BCR 0
+
+/* VIDEO_CC GDSCRs */
+#define VENUS_GDSC 0
+#define VCODEC0_GDSC 1
+#define VCODEC1_GDSC 2
+
+#endif