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| author | Stephen Warren <swarren@nvidia.com> | 2012-07-24 23:48:12 +0200 |
|---|---|---|
| committer | Stephen Warren <swarren@nvidia.com> | 2012-09-06 19:47:19 +0200 |
| commit | eb70e1bdd8a633e058cfb6186d45d4c8bdbdf534 (patch) | |
| tree | 9c59a67a6100ca90d94a202aeff0a7c7c48ee042 | |
| parent | ARM: tegra: turn on UART A clock at boot (diff) | |
| download | linux-eb70e1bdd8a633e058cfb6186d45d4c8bdbdf534.tar.xz linux-eb70e1bdd8a633e058cfb6186d45d4c8bdbdf534.zip | |
ARM: tegra: fix U16 divider range check
A U16 divider can divide a clock by 1..64K. However, the range-check
in clk_div16_get_divider() limited the range to 1..256. Fix this. NVIDIA's
downstream kernels already have the fixed range-check.
In practice this is a problem on Whistler's I2C bus, which uses a bus
clock rate of 100KHz (rather than the more common 400KHz on Tegra boards),
which requires a HW module clock of 8*100KHz. The parent clock is 216MHz,
leading to a desired divider of 270. Prior to conversion to the common
clock framework, this range error was somehow ignored/irrelevant and
caused no problems. However, the common clock framework evidently has
more rigorous error-checking, so this failure causes the I2C bus to fail
to operate correctly.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
| -rw-r--r-- | arch/arm/mach-tegra/tegra2_clocks.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-tegra/tegra2_clocks.c b/arch/arm/mach-tegra/tegra2_clocks.c index a703844b2061..83ccb85b9405 100644 --- a/arch/arm/mach-tegra/tegra2_clocks.c +++ b/arch/arm/mach-tegra/tegra2_clocks.c @@ -223,7 +223,7 @@ static int clk_div16_get_divider(unsigned long parent_rate, unsigned long rate) if (divider_u16 - 1 < 0) return 0; - if (divider_u16 - 1 > 255) + if (divider_u16 - 1 > 0xFFFF) return -EINVAL; return divider_u16 - 1; |