diff options
| author | Andre Przywara <andre.przywara@arm.com> | 2019-01-23 01:59:11 +0100 |
|---|---|---|
| committer | Maxime Ripard <maxime.ripard@bootlin.com> | 2019-01-28 09:26:32 +0100 |
| commit | ee0b27a3a4da0b0ed2318aa092f8856896e9450b (patch) | |
| tree | 37dac0f2b5e3a838c099b1efe1d02f75e986f6bb | |
| parent | clk: sunxi-ng: v3s: Fix TCON reset de-assert bit (diff) | |
| download | linux-ee0b27a3a4da0b0ed2318aa092f8856896e9450b.tar.xz linux-ee0b27a3a4da0b0ed2318aa092f8856896e9450b.zip | |
clk: sunxi: A31: Fix wrong AHB gate number
According to the manual the gate clock for MMC3 is at bit 11, and NAND1
is controlled by bit 12.
Fix the gate bit definitions in the clock driver.
Fixes: c6e6c96d8fa6 ("clk: sunxi-ng: Add A31/A31s clocks")
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
| -rw-r--r-- | drivers/clk/sunxi-ng/ccu-sun6i-a31.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c index 3b97f60540ad..609970c0b666 100644 --- a/drivers/clk/sunxi-ng/ccu-sun6i-a31.c +++ b/drivers/clk/sunxi-ng/ccu-sun6i-a31.c @@ -264,9 +264,9 @@ static SUNXI_CCU_GATE(ahb1_mmc1_clk, "ahb1-mmc1", "ahb1", static SUNXI_CCU_GATE(ahb1_mmc2_clk, "ahb1-mmc2", "ahb1", 0x060, BIT(10), 0); static SUNXI_CCU_GATE(ahb1_mmc3_clk, "ahb1-mmc3", "ahb1", - 0x060, BIT(12), 0); + 0x060, BIT(11), 0); static SUNXI_CCU_GATE(ahb1_nand1_clk, "ahb1-nand1", "ahb1", - 0x060, BIT(13), 0); + 0x060, BIT(12), 0); static SUNXI_CCU_GATE(ahb1_nand0_clk, "ahb1-nand0", "ahb1", 0x060, BIT(13), 0); static SUNXI_CCU_GATE(ahb1_sdram_clk, "ahb1-sdram", "ahb1", |