diff options
| author | Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> | 2023-10-10 15:26:56 +0200 |
|---|---|---|
| committer | Geert Uytterhoeven <geert+renesas@glider.be> | 2023-10-12 20:05:36 +0200 |
| commit | fd627207aaa782c1fd4224076b56a03a1059f516 (patch) | |
| tree | a3e1913d6fabc8aa2789bba0bcbf25a55967e57e | |
| parent | clk: renesas: Add minimal boot support for RZ/G3S SoC (diff) | |
| download | linux-fd627207aaa782c1fd4224076b56a03a1059f516.tar.xz linux-fd627207aaa782c1fd4224076b56a03a1059f516.zip | |
clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()
Use the %x format specifier to print CLK_ON_R(). This makes debugging
easier as the value printed will be hexadecimal like in the hardware
manual. Along with it add "0x" in front of the printed value.
Signed-off-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20231010132701.1658737-2-claudiu.beznea.uj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
| -rw-r--r-- | drivers/clk/renesas/rzg2l-cpg.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c index d62f1bc1f60e..764bd72cf059 100644 --- a/drivers/clk/renesas/rzg2l-cpg.c +++ b/drivers/clk/renesas/rzg2l-cpg.c @@ -1213,7 +1213,7 @@ static int rzg2l_mod_clock_endisable(struct clk_hw *hw, bool enable) return 0; } - dev_dbg(dev, "CLK_ON %u/%pC %s\n", CLK_ON_R(reg), hw->clk, + dev_dbg(dev, "CLK_ON 0x%x/%pC %s\n", CLK_ON_R(reg), hw->clk, enable ? "ON" : "OFF"); value = bitmask << 16; |