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authorCédric Le Goater <clg@kaod.org>2019-04-18 12:39:35 +0200
committerPaul Mackerras <paulus@ozlabs.org>2019-04-30 11:35:16 +0200
commite4945b9da52b36052b7c509ca31c5ead1d165b24 (patch)
treeea7e9816f2a88dacd6988983c126455d7eec79a0 /Documentation/SAK.txt
parentKVM: PPC: Book3S HV: XIVE: Add a control to dirty the XIVE EQ pages (diff)
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KVM: PPC: Book3S HV: XIVE: Add get/set accessors for the VP XIVE state
The state of the thread interrupt management registers needs to be collected for migration. These registers are cached under the 'xive_saved_state.w01' field of the VCPU when the VPCU context is pulled from the HW thread. An OPAL call retrieves the backup of the IPB register in the underlying XIVE NVT structure and merges it in the KVM state. Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: David Gibson <david@gibson.dropbear.id.au> Signed-off-by: Paul Mackerras <paulus@ozlabs.org>
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