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authorMaxime Ripard <maxime@cerno.tech>2019-12-19 10:07:10 +0100
committerRob Herring <robh@kernel.org>2019-12-24 22:17:52 +0100
commitf95cad74acdb9de3b61a95ae8203c5e78b7d3615 (patch)
tree38fd9801311a90bb3f36be28c4d3e6c097213427 /Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml
parentdt-bindings: opp: Convert Allwinner H6 OPP to a schema (diff)
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dt-bindings: clocks: Convert Allwinner legacy clocks to schemas
The Allwinner SoCs have a legacy set of bindings (and a framework to support it in Linux) for their clock controllers. Now that we have the DT validation in place, let's split into separate file and convert the device tree bindings for those clocks to schemas, and mark them all as deprecated. Signed-off-by: Maxime Ripard <maxime@cerno.tech> Signed-off-by: Rob Herring <robh@kernel.org>
Diffstat (limited to 'Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml')
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diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml
new file mode 100644
index 000000000000..415bd77de53d
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+++ b/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-pll5-clk.yaml
@@ -0,0 +1,53 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/allwinner,sun4i-a10-pll5-clk.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Allwinner A10 DRAM PLL Device Tree Bindings
+
+maintainers:
+ - Chen-Yu Tsai <wens@csie.org>
+ - Maxime Ripard <mripard@kernel.org>
+
+deprecated: true
+
+properties:
+ "#clock-cells":
+ const: 1
+ description: >
+ The first output is the DRAM clock output, the second is meant
+ for peripherals on the SoC.
+
+ compatible:
+ const: allwinner,sun4i-a10-pll5-clk
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-output-names:
+ maxItems: 2
+
+required:
+ - "#clock-cells"
+ - compatible
+ - reg
+ - clocks
+ - clock-output-names
+
+additionalProperties: false
+
+examples:
+ - |
+ clk@1c20020 {
+ #clock-cells = <1>;
+ compatible = "allwinner,sun4i-a10-pll5-clk";
+ reg = <0x01c20020 0x4>;
+ clocks = <&osc24M>;
+ clock-output-names = "pll5_ddr", "pll5_other";
+ };
+
+...