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authorDmitry Torokhov <dmitry.torokhov@gmail.com>2013-07-02 18:01:31 +0200
committerDmitry Torokhov <dmitry.torokhov@gmail.com>2013-07-02 18:01:31 +0200
commit27eb2c4b3d3e13f376a359e293c212a2e9407af5 (patch)
tree556aa7b5cd6eeb4214dec129c789515157187010 /Documentation/devicetree/bindings/cpufreq/arm_big_little_dt.txt
parentInput: tps6507x-ts - convert to polled input device infrastructure (diff)
parentInput: cyttsp4 - SPI driver for Cypress TMA4XX touchscreen devices (diff)
downloadlinux-27eb2c4b3d3e13f376a359e293c212a2e9407af5.tar.xz
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Merge branch 'next' into for-linus
Prepare first set of updates for 3.11 merge window.
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+Generic ARM big LITTLE cpufreq driver's DT glue
+-----------------------------------------------
+
+This is DT specific glue layer for generic cpufreq driver for big LITTLE
+systems.
+
+Both required and optional properties listed below must be defined
+under node /cpus/cpu@x. Where x is the first cpu inside a cluster.
+
+FIXME: Cpus should boot in the order specified in DT and all cpus for a cluster
+must be present contiguously. Generic DT driver will check only node 'x' for
+cpu:x.
+
+Required properties:
+- operating-points: Refer to Documentation/devicetree/bindings/power/opp.txt
+ for details
+
+Optional properties:
+- clock-latency: Specify the possible maximum transition latency for clock,
+ in unit of nanoseconds.
+
+Examples:
+
+cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu@0 {
+ compatible = "arm,cortex-a15";
+ reg = <0>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 792000 1100000
+ 396000 950000
+ 198000 850000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ };
+
+ cpu@1 {
+ compatible = "arm,cortex-a15";
+ reg = <1>;
+ next-level-cache = <&L2>;
+ };
+
+ cpu@100 {
+ compatible = "arm,cortex-a7";
+ reg = <100>;
+ next-level-cache = <&L2>;
+ operating-points = <
+ /* kHz uV */
+ 792000 950000
+ 396000 750000
+ 198000 450000
+ >;
+ clock-latency = <61036>; /* two CLK32 periods */
+ };
+
+ cpu@101 {
+ compatible = "arm,cortex-a7";
+ reg = <101>;
+ next-level-cache = <&L2>;
+ };
+};