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authorThierry Reding <treding@nvidia.com>2019-01-25 11:00:57 +0100
committerThierry Reding <treding@nvidia.com>2019-02-07 18:29:01 +0100
commit6c2b3881d0df85fed7e3f43dcc9cbc3e5124bc12 (patch)
treebc3e591335d308338cc22e0fefa4bd0cf9577d32 /Documentation/devicetree/bindings/display/tegra
parentdrm/tegra: vic: Support stream ID register programming (diff)
downloadlinux-6c2b3881d0df85fed7e3f43dcc9cbc3e5124bc12.tar.xz
linux-6c2b3881d0df85fed7e3f43dcc9cbc3e5124bc12.zip
dt-bindings: display: tegra: Support SOR crossbar configuration
The SOR has a crossbar that can map each lane of the SOR to each of the SOR pads. The mapping is usually the same across designs for a specific SoC generation, but every now and then there's a design that doesn't. Allow the crossbar configuration to be specified in device tree to make it possible to support these designs. Signed-off-by: Thierry Reding <treding@nvidia.com>
Diffstat (limited to 'Documentation/devicetree/bindings/display/tegra')
-rw-r--r--Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt3
1 files changed, 3 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
index 593be44a53c9..9999255ac5b6 100644
--- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
+++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-host1x.txt
@@ -238,6 +238,9 @@ of the following host1x client modules:
- nvidia,hpd-gpio: specifies a GPIO used for hotplug detection
- nvidia,edid: supplies a binary EDID blob
- nvidia,panel: phandle of a display panel
+ - nvidia,xbar-cfg: 5 cells containing the crossbar configuration. Each lane
+ of the SOR, identified by the cell's index, is mapped via the crossbar to
+ the pad specified by the cell's value.
Optional properties when driving an eDP output:
- nvidia,dpaux: phandle to a DispayPort AUX interface