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author | Kun Yi <kunyi@google.com> | 2020-12-11 22:54:27 +0100 |
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committer | Guenter Roeck <linux@roeck-us.net> | 2020-12-12 17:36:09 +0100 |
commit | 1a033769a4fe9a86ee791fd553b6a996dd76e026 (patch) | |
tree | 2218a3a585bc74b37308bd0c2b97cb1201e36766 /Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml | |
parent | hwmon: (sbtsi) Add documentation (diff) | |
download | linux-1a033769a4fe9a86ee791fd553b6a996dd76e026.tar.xz linux-1a033769a4fe9a86ee791fd553b6a996dd76e026.zip |
dt-bindings: (hwmon/sbtsi_temp) Add SB-TSI hwmon driver bindings
Document device tree bindings for AMD SB-TSI emulated temperature
sensor.
Signed-off-by: Kun Yi <kunyi@google.com>
Link: https://lore.kernel.org/r/20201211215427.3281681-4-kunyi@google.com
Reviewed-by: Rob Herring <robh@kernel.org>
[groeck: Fixed subject]
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
Diffstat (limited to 'Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml')
-rw-r--r-- | Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml | 54 |
1 files changed, 54 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml new file mode 100644 index 000000000000..446b09f1ce94 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/amd,sbtsi.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/amd,sbtsi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: > + Sideband interface Temperature Sensor Interface (SB-TSI) compliant + AMD SoC temperature device + +maintainers: + - Kun Yi <kunyi@google.com> + - Supreeth Venkatesh <supreeth.venkatesh@amd.com> + +description: | + SB Temperature Sensor Interface (SB-TSI) is an SMBus compatible + interface that reports AMD SoC's Ttcl (normalized temperature), + and resembles a typical 8-pin remote temperature sensor's I2C interface + to BMC. The emulated thermal sensor can report temperatures in increments + of 0.125 degrees, ranging from 0 to 255.875. + +properties: + compatible: + enum: + - amd,sbtsi + + reg: + maxItems: 1 + description: | + I2C bus address of the device as specified in Section 6.3.1 of the + SoC register reference. The SB-TSI address is normally 98h for socket + 0 and 90h for socket 1, but it could vary based on hardware address + select pins. + \[open source SoC register reference\] + https://www.amd.com/system/files/TechDocs/56255_OSRR.pdf + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + i2c0 { + #address-cells = <1>; + #size-cells = <0>; + + sbtsi@4c { + compatible = "amd,sbtsi"; + reg = <0x4c>; + }; + }; +... |