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authorAndi Kleen <ak@suse.de>2005-07-29 06:15:34 +0200
committerLinus Torvalds <torvalds@g5.osdl.org>2005-07-29 06:45:59 +0200
commitef4d7cbea773a77b36e732779cab4018ba2c037b (patch)
treec9aeb9e716ee2d83204724d6e2baa2b2e81caf0e /Documentation/x86_64
parent[PATCH] x86_64: Improve CONFIG_GART_IOMMU description and make it default y (diff)
downloadlinux-ef4d7cbea773a77b36e732779cab4018ba2c037b.tar.xz
linux-ef4d7cbea773a77b36e732779cab4018ba2c037b.zip
[PATCH] x86_64: Some updates for boot-options.txt
Signed-off-by: Andi Kleen <ak@suse.de> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Diffstat (limited to 'Documentation/x86_64')
-rw-r--r--Documentation/x86_64/boot-options.txt10
1 files changed, 6 insertions, 4 deletions
diff --git a/Documentation/x86_64/boot-options.txt b/Documentation/x86_64/boot-options.txt
index b9e6be00cadf..476c0c22fbb7 100644
--- a/Documentation/x86_64/boot-options.txt
+++ b/Documentation/x86_64/boot-options.txt
@@ -47,7 +47,7 @@ Timing
notsc
Don't use the CPU time stamp counter to read the wall time.
This can be used to work around timing problems on multiprocessor systems
- with not properly synchronized CPUs. Only useful with a SMP kernel
+ with not properly synchronized CPUs.
report_lost_ticks
Report when timer interrupts are lost because some code turned off
@@ -74,6 +74,9 @@ Idle loop
event. This will make the CPUs eat a lot more power, but may be useful
to get slightly better performance in multiprocessor benchmarks. It also
makes some profiling using performance counters more accurate.
+ Please note that on systems with MONITOR/MWAIT support (like Intel EM64T
+ CPUs) this option has no performance advantage over the normal idle loop.
+ It may also interact badly with hyperthreading.
Rebooting
@@ -178,6 +181,5 @@ Debugging
Misc
noreplacement Don't replace instructions with more appropiate ones
- for the CPU. This may be useful on asymmetric MP systems
- where some CPU have less capabilities than the others.
-
+ for the CPU. This may be useful on asymmetric MP systems
+ where some CPU have less capabilities than the others.