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| author | Robin Murphy <Robin.Murphy@arm.com> | 2015-07-29 20:46:05 +0200 |
|---|---|---|
| committer | Will Deacon <will.deacon@arm.com> | 2015-07-31 12:42:53 +0200 |
| commit | bae2c2d421cdea9dd8d62425eef99e389584cdb3 (patch) | |
| tree | 1bffdcbb32e05ed42cd7268ec47325845d67428e /Documentation | |
| parent | iommu/arm-smmu: Limit 2-level strtab allocation for small SID sizes (diff) | |
| download | linux-bae2c2d421cdea9dd8d62425eef99e389584cdb3.tar.xz linux-bae2c2d421cdea9dd8d62425eef99e389584cdb3.zip | |
iommu/arm-smmu: Sort out coherency
Currently, we detect whether the SMMU has coherent page table walk
capability from the IDR0.CTTW field, and base our cache maintenance
decisions on that. In preparation for fixing the bogus DMA API usage,
however, we need to ensure that the DMA API agrees about this, which
necessitates deferring to the dma-coherent property in the device tree
for the final say.
As an added bonus, since systems exist where an external CTTW signal
has been tied off incorrectly at integration, allowing DT to override
it offers a neat workaround for coherency issues with such SMMUs.
Signed-off-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Diffstat (limited to 'Documentation')
| -rw-r--r-- | Documentation/devicetree/bindings/iommu/arm,smmu.txt | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/Documentation/devicetree/bindings/iommu/arm,smmu.txt b/Documentation/devicetree/bindings/iommu/arm,smmu.txt index 06760503a819..718074501fcb 100644 --- a/Documentation/devicetree/bindings/iommu/arm,smmu.txt +++ b/Documentation/devicetree/bindings/iommu/arm,smmu.txt @@ -43,6 +43,12 @@ conditions. ** System MMU optional properties: +- dma-coherent : Present if page table walks made by the SMMU are + cache coherent with the CPU. + + NOTE: this only applies to the SMMU itself, not + masters connected upstream of the SMMU. + - calxeda,smmu-secure-config-access : Enable proper handling of buggy implementations that always use secure access to SMMU configuration registers. In this case non-secure |