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authorDave Gerlach <d-gerlach@ti.com>2017-03-06 16:23:41 +0100
committerTony Lindgren <tony@atomide.com>2017-03-23 21:45:12 +0100
commita4e5e9f93854845e87dd8debed07afdb0b844412 (patch)
treeca1e6fe9585dc935a1df093e9a022d6e67b96c53 /arch/arm/boot/dts/dra74x.dtsi
parentARM: dts: am4372: Update operating-points-v2 table for cpu (diff)
downloadlinux-a4e5e9f93854845e87dd8debed07afdb0b844412.tar.xz
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ARM: dts: dra7: Add updated operating-points-v2 table for cpu
After the ti-cpufreq driver has been added, we can now drop the operating-points table present in dra7.dtsi for the cpu and add an operating-points-v2 table with all OPPs available for all silicon revisions. Also add necessary data for use by ti-cpufreq to selectively enable the appropriate OPPs at runtime as part of the operating-points table. As we now need to define voltage ranges for each OPP, we define the minimum and maximum voltage to match the ranges possible for AVS class0 voltage as defined by the DRA7/AM57 Data Manual, with the exception of using a range for OPP_OD based on historical data to ensure that SoCs from older lots still continue to boot, even though more optimal voltages are now the standard. Once an AVS Class0 driver is in place it will be possible for these OPP voltages to be adjusted to any voltage within the provided range. Information from SPRS953, Revised December 2015. Signed-off-by: Dave Gerlach <d-gerlach@ti.com> eviewed-by: Lukasz Majewski <lukma@denx.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Tony Lindgren <tony@atomide.com>
Diffstat (limited to 'arch/arm/boot/dts/dra74x.dtsi')
-rw-r--r--arch/arm/boot/dts/dra74x.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/dra74x.dtsi b/arch/arm/boot/dts/dra74x.dtsi
index 0a78347e6615..24e6746c5b26 100644
--- a/arch/arm/boot/dts/dra74x.dtsi
+++ b/arch/arm/boot/dts/dra74x.dtsi
@@ -17,6 +17,7 @@
device_type = "cpu";
compatible = "arm,cortex-a15";
reg = <1>;
+ operating-points-v2 = <&cpu0_opp_table>;
};
};
@@ -79,6 +80,10 @@
};
};
+&cpu0_opp_table {
+ opp-shared;
+};
+
&dss {
reg = <0x58000000 0x80>,
<0x58004054 0x4>,