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authorViresh Kumar <viresh.kumar@linaro.org>2018-11-16 11:01:10 +0100
committerKrzysztof Kozlowski <krzk@kernel.org>2018-11-18 15:17:08 +0100
commit670734f5581023a2e695e82ea662e4d603fd3e8a (patch)
treed7c91412ccf452f6ecb0f8e1e7109b5b1fab6607 /arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
parentARM: dts: exynos: Clarify comment explaining purpose of Odroid XU3 DTSI (diff)
downloadlinux-670734f5581023a2e695e82ea662e4d603fd3e8a.tar.xz
linux-670734f5581023a2e695e82ea662e4d603fd3e8a.zip
ARM: dts: exynos: Add all CPUs in cooling maps
Each CPU can (and does) participate in cooling down the system but the DT only captures a handful of them, normally CPU0, in the cooling maps. Things work by chance currently as under normal circumstances its the first CPU of each cluster which is used by the operating systems to probe the cooling devices. But as soon as this CPU ordering changes and any other CPU is used to bring up the cooling device, we will start seeing failures. Also the DT is rather incomplete when we list only one CPU in the cooling maps, as the hardware doesn't have any such limitations. Update cooling maps to include all devices affected by individual trip points. Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi8
1 files changed, 6 insertions, 2 deletions
diff --git a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
index 8fdfd80c3acc..0038465f38f1 100644
--- a/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
+++ b/arch/arm/boot/dts/exynos4412-itop-scp-core.dtsi
@@ -45,11 +45,15 @@
cooling-maps {
map0 {
/* Corresponds to 800MHz at freq_table */
- cooling-device = <&cpu0 7 7>;
+ cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
+ <&cpu2 7 7>, <&cpu3 7 7>;
};
map1 {
/* Corresponds to 200MHz at freq_table */
- cooling-device = <&cpu0 13 13>;
+ cooling-device = <&cpu0 13 13>,
+ <&cpu1 13 13>,
+ <&cpu2 13 13>,
+ <&cpu3 13 13>;
};
};
};