summaryrefslogtreecommitdiffstats
path: root/arch/arm/boot/dts/exynos5420.dtsi
diff options
context:
space:
mode:
authorMarek Szyprowski <m.szyprowski@samsung.com>2017-01-30 13:19:00 +0100
committerKrzysztof Kozlowski <krzk@kernel.org>2017-01-31 20:30:48 +0100
commit55d74adfa9758cad5dd989b22cb2558303fe9a0f (patch)
treee199c800992e538bfaaffbb9deac67994e738815 /arch/arm/boot/dts/exynos5420.dtsi
parentARM: dts: exynos: Fix indentation of EHCI and OHCI ports (diff)
downloadlinux-55d74adfa9758cad5dd989b22cb2558303fe9a0f.tar.xz
linux-55d74adfa9758cad5dd989b22cb2558303fe9a0f.zip
ARM: dts: exynos: Add labels to all existing power domains
Provide human readable names for all power domains defined in Exynos SoCs. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Diffstat (limited to 'arch/arm/boot/dts/exynos5420.dtsi')
-rw-r--r--arch/arm/boot/dts/exynos5420.dtsi5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/exynos5420.dtsi b/arch/arm/boot/dts/exynos5420.dtsi
index 0154c2e373f8..7dc9dc82afd8 100644
--- a/arch/arm/boot/dts/exynos5420.dtsi
+++ b/arch/arm/boot/dts/exynos5420.dtsi
@@ -277,6 +277,7 @@
compatible = "samsung,exynos4210-pd";
reg = <0x10044000 0x20>;
#power-domain-cells = <0>;
+ label = "GSC";
clocks = <&clock CLK_FIN_PLL>,
<&clock CLK_MOUT_USER_ACLK300_GSCL>,
<&clock CLK_GSCL0>, <&clock CLK_GSCL1>;
@@ -287,6 +288,7 @@
compatible = "samsung,exynos4210-pd";
reg = <0x10044020 0x20>;
#power-domain-cells = <0>;
+ label = "ISP";
};
mfc_pd: power-domain@10044060 {
@@ -297,18 +299,21 @@
<&clock CLK_ACLK333>;
clock-names = "oscclk", "clk0","asb0";
#power-domain-cells = <0>;
+ label = "MFC";
};
msc_pd: power-domain@10044120 {
compatible = "samsung,exynos4210-pd";
reg = <0x10044120 0x20>;
#power-domain-cells = <0>;
+ label = "MSC";
};
disp_pd: power-domain@100440C0 {
compatible = "samsung,exynos4210-pd";
reg = <0x100440C0 0x20>;
#power-domain-cells = <0>;
+ label = "DISP";
clocks = <&clock CLK_FIN_PLL>,
<&clock CLK_MOUT_USER_ACLK200_DISP1>,
<&clock CLK_MOUT_USER_ACLK300_DISP1>,