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| author | Cristian Ciocaltea <cristian.ciocaltea@gmail.com> | 2020-12-29 22:17:17 +0100 |
|---|---|---|
| committer | Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> | 2020-12-31 08:35:06 +0100 |
| commit | 11bc96ba758bf05a8048522d477c5953176132c9 (patch) | |
| tree | 340014c5802330bb0e1d4ed408c4c4af32482e31 /arch/arm/boot/dts/owl-s500-roseapplepi.dts | |
| parent | arm: dts: owl-s500: Add Clock Management Unit (diff) | |
| download | linux-11bc96ba758bf05a8048522d477c5953176132c9.tar.xz linux-11bc96ba758bf05a8048522d477c5953176132c9.zip | |
arm: dts: owl-s500: Set CMU clocks for UARTs
Set Clock Management Unit clocks for the UART nodes of Actions Semi
S500 SoCs and remove the dummy "uart2_clk" and "uart3_clk" fixed clocks.
Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Diffstat (limited to 'arch/arm/boot/dts/owl-s500-roseapplepi.dts')
| -rw-r--r-- | arch/arm/boot/dts/owl-s500-roseapplepi.dts | 7 |
1 files changed, 0 insertions, 7 deletions
diff --git a/arch/arm/boot/dts/owl-s500-roseapplepi.dts b/arch/arm/boot/dts/owl-s500-roseapplepi.dts index a2087e617cb2..800edf5d2d12 100644 --- a/arch/arm/boot/dts/owl-s500-roseapplepi.dts +++ b/arch/arm/boot/dts/owl-s500-roseapplepi.dts @@ -25,12 +25,6 @@ device_type = "memory"; reg = <0x0 0x80000000>; /* 2GB */ }; - - uart2_clk: uart2-clk { - compatible = "fixed-clock"; - clock-frequency = <921600>; - #clock-cells = <0>; - }; }; &twd_timer { @@ -43,5 +37,4 @@ &uart2 { status = "okay"; - clocks = <&uart2_clk>; }; |