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| author | Rohit Agarwal <quic_rohiagar@quicinc.com> | 2022-03-16 07:17:25 +0100 |
|---|---|---|
| committer | Bjorn Andersson <bjorn.andersson@linaro.org> | 2022-04-13 05:29:40 +0200 |
| commit | 52fedb2f324d9be967cf760dcdc894b37f5a95d9 (patch) | |
| tree | 978d811047f642d1b8e9a1d2b0003ba73d3446fd /arch/arm/boot/dts/qcom-sdx65.dtsi | |
| parent | ARM: dts: qcom: sdx65-mtp: Add pmx65 pmic (diff) | |
| download | linux-52fedb2f324d9be967cf760dcdc894b37f5a95d9.tar.xz linux-52fedb2f324d9be967cf760dcdc894b37f5a95d9.zip | |
ARM: dts: qcom: sdx65: Add rpmpd node
Add rpmpd node and opps for this node to the SDX65 dts.
Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1647411447-25249-5-git-send-email-quic_rohiagar@quicinc.com
Diffstat (limited to 'arch/arm/boot/dts/qcom-sdx65.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/qcom-sdx65.dtsi | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/arm/boot/dts/qcom-sdx65.dtsi b/arch/arm/boot/dts/qcom-sdx65.dtsi index ba7b6c5c1562..7e2697f1e665 100644 --- a/arch/arm/boot/dts/qcom-sdx65.dtsi +++ b/arch/arm/boot/dts/qcom-sdx65.dtsi @@ -9,6 +9,7 @@ #include <dt-bindings/clock/qcom,gcc-sdx65.h> #include <dt-bindings/clock/qcom,rpmh.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/power/qcom-rpmpd.h> #include <dt-bindings/soc/qcom,rpmh-rsc.h> / { @@ -244,6 +245,56 @@ clock-names = "xo"; clocks = <&xo_board>; }; + + rpmhpd: power-controller { + compatible = "qcom,sdx65-rpmhpd"; + #power-domain-cells = <1>; + operating-points-v2 = <&rpmhpd_opp_table>; + + rpmhpd_opp_table: opp-table { + compatible = "operating-points-v2"; + + rpmhpd_opp_ret: opp1 { + opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; + }; + + rpmhpd_opp_min_svs: opp2 { + opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; + }; + + rpmhpd_opp_low_svs: opp3 { + opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; + }; + + rpmhpd_opp_svs: opp4 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS>; + }; + + rpmhpd_opp_svs_l1: opp5 { + opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; + }; + + rpmhpd_opp_nom: opp6 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM>; + }; + + rpmhpd_opp_nom_l1: opp7 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; + }; + + rpmhpd_opp_nom_l2: opp8 { + opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; + }; + + rpmhpd_opp_turbo: opp9 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; + }; + + rpmhpd_opp_turbo_l1: opp10 { + opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; + }; + }; + }; }; }; |