diff options
| author | Geert Uytterhoeven <geert+renesas@glider.be> | 2014-11-05 11:04:34 +0100 |
|---|---|---|
| committer | Simon Horman <horms+renesas@verge.net.au> | 2014-11-10 01:56:01 +0100 |
| commit | b89ff7c3c2dee189489a5f45eb8d72e106179299 (patch) | |
| tree | 7ac9b5f8c4a8efa7a8351154d175edbbbda1ab89 /arch/arm/boot/dts/r8a7740.dtsi | |
| parent | ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree (diff) | |
| download | linux-b89ff7c3c2dee189489a5f45eb8d72e106179299.tar.xz linux-b89ff7c3c2dee189489a5f45eb8d72e106179299.zip | |
ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock
According to the datasheet, the operating clock for IIC0 is the HPP
(RT Peri) clock, not the SUB (Peri) clock. Both clocks run at the same
speed (50 Mhz).
This is consistent with IIC0 being located in the A4R PM domain, and
IIC1 in the A3SP PM domain.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Diffstat (limited to 'arch/arm/boot/dts/r8a7740.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/r8a7740.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/boot/dts/r8a7740.dtsi b/arch/arm/boot/dts/r8a7740.dtsi index d46c213a17ad..eed697a6bd6b 100644 --- a/arch/arm/boot/dts/r8a7740.dtsi +++ b/arch/arm/boot/dts/r8a7740.dtsi @@ -433,7 +433,7 @@ clocks = <&cpg_clocks R8A7740_CLK_S>, <&cpg_clocks R8A7740_CLK_S>, <&sub_clk>, <&cpg_clocks R8A7740_CLK_B>, - <&sub_clk>, <&sub_clk>, + <&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>, <&cpg_clocks R8A7740_CLK_B>; #clock-cells = <1>; renesas,clock-indices = < |