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| author | Heiko Stuebner <heiko@sntech.de> | 2016-03-26 22:49:57 +0100 |
|---|---|---|
| committer | Heiko Stuebner <heiko@sntech.de> | 2016-08-08 10:56:55 +0200 |
| commit | 546a3521f251462128d877e48fb3544c74976ce4 (patch) | |
| tree | d334ae734bf38fd4e65c50156c95b47415b89184 /arch/arm/boot/dts/rk3288.dtsi | |
| parent | ARM: dts: rockchip: add rk3288-firefly-reload (diff) | |
| download | linux-546a3521f251462128d877e48fb3544c74976ce4.tar.xz linux-546a3521f251462128d877e48fb3544c74976ce4.zip | |
ARM: dts: rockchip: move rk3288 usbphy under the GRF node
The rk3288 usbphy is completely enclosed in the general register files
and the updated binding allows it to be a subnode of the GRF now.
So move the node appropriately.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Diffstat (limited to 'arch/arm/boot/dts/rk3288.dtsi')
| -rw-r--r-- | arch/arm/boot/dts/rk3288.dtsi | 63 |
1 files changed, 31 insertions, 32 deletions
diff --git a/arch/arm/boot/dts/rk3288.dtsi b/arch/arm/boot/dts/rk3288.dtsi index cd33f0170890..e5c4a11f6bc6 100644 --- a/arch/arm/boot/dts/rk3288.dtsi +++ b/arch/arm/boot/dts/rk3288.dtsi @@ -832,6 +832,37 @@ compatible = "rockchip,rk3288-io-voltage-domain"; status = "disabled"; }; + + usbphy: usbphy { + compatible = "rockchip,rk3288-usb-phy"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + + usbphy0: usb-phy@320 { + #phy-cells = <0>; + reg = <0x320>; + clocks = <&cru SCLK_OTGPHY0>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy1: usb-phy@334 { + #phy-cells = <0>; + reg = <0x334>; + clocks = <&cru SCLK_OTGPHY1>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + + usbphy2: usb-phy@348 { + #phy-cells = <0>; + reg = <0x348>; + clocks = <&cru SCLK_OTGPHY2>; + clock-names = "phyclk"; + #clock-cells = <0>; + }; + }; }; wdt: watchdog@ff800000 { @@ -1085,38 +1116,6 @@ }; }; - usbphy: phy { - compatible = "rockchip,rk3288-usb-phy"; - rockchip,grf = <&grf>; - #address-cells = <1>; - #size-cells = <0>; - status = "disabled"; - - usbphy0: usb-phy@320 { - #phy-cells = <0>; - reg = <0x320>; - clocks = <&cru SCLK_OTGPHY0>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy1: usb-phy@334 { - #phy-cells = <0>; - reg = <0x334>; - clocks = <&cru SCLK_OTGPHY1>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - - usbphy2: usb-phy@348 { - #phy-cells = <0>; - reg = <0x348>; - clocks = <&cru SCLK_OTGPHY2>; - clock-names = "phyclk"; - #clock-cells = <0>; - }; - }; - pinctrl: pinctrl { compatible = "rockchip,rk3288-pinctrl"; rockchip,grf = <&grf>; |